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71. 发明申请

US20080220584A1 Methods of Forming Integrated Circuit Structures Using Insulator Deposition and Insulator Gap Filling Techniques 有权
标题翻译：使用绝缘体沉积和绝缘子间隙填充技术形成集成电路结构的方法
公开(公告)号：US20080220584A1
公开(公告)日：2008-09-11
申请号：US11683590
申请日：2007-03-08
申请人： Jun-jung Kim , Ja-hum Ku , Jae-eon Park , Sunfei Fang , Alois Gutmann , O-sung Kwon , Johnny Widodo , Dae-won Yang
发明人： Jun-jung Kim , Ja-hum Ku , Jae-eon Park , Sunfei Fang , Alois Gutmann , O-sung Kwon , Johnny Widodo , Dae-won Yang
IPC分类号： H01L29/82
CPC分类号： H01L21/0217 , C23C16/56 , H01L21/02211 , H01L21/02266 , H01L21/02274 , H01L21/31051 , H01L21/3185 , H01L21/76826 , H01L21/76829 , H01L21/76837 , H01L21/823425
摘要： Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.
摘要翻译：形成集成电路器件的方法包括在其上具有集成电路结构的集成电路衬底上沉积电绝缘层。该沉积步骤导致形成具有起伏表面轮廓的电绝缘层，该电绝缘层包括至少一个峰和至少与至少一个峰相邻的峰。然后进行非均匀的增稠步骤。这种不均匀的增厚步骤包括通过将电绝缘层的部分从至少一个峰重新沉积到至少一个谷部来增厚电绝缘层的一部分。使用利用电绝缘层作为溅射靶的溅射沉积技术发生这种再沉积。

72. 发明申请

US20080119019A1 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same 有权
标题翻译：具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法
公开(公告)号：US20080119019A1
公开(公告)日：2008-05-22
申请号：US11602117
申请日：2006-11-20
申请人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
发明人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
IPC分类号： H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L29/66636 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
摘要翻译：在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

73. 发明申请

US20070190795A1 Method for fabricating a semiconductor device with a high-K dielectric 审中-公开
标题翻译：制造具有高K电介质的半导体器件的方法
公开(公告)号：US20070190795A1
公开(公告)日：2007-08-16
申请号：US11352565
申请日：2006-02-13
申请人： Haoren Zhuang , Jiang Yan , Jin-Ping Han , Jingyu Lian , Alois Gutmann
发明人： Haoren Zhuang , Jiang Yan , Jin-Ping Han , Jingyu Lian , Alois Gutmann
IPC分类号： H01L21/302
CPC分类号： H01L21/0206 , H01L21/28123 , H01L29/513 , H01L29/517
摘要： Method for fabricating semiconductor devices with high-K materials without the presence of undesired formations of the high-K material. A preferred embodiment comprises forming a layer of material over a layer of a high-K material, etching the layer of material to expose a portion of the high-K material, performing a CDE (Chemical Downstream Etch) to remove any residual material formed during the etching, and etching the layer of the high-K material into alignment with remaining portions of the layer of material. The removal of the residual material results in a predictable trimming of the high-K material so that the semiconductor device has predictable and consistent performance, which is not possible if the high-K material has unpredictable dimensions.
摘要翻译：用于制造具有高K材料的半导体器件的方法，而不存在不需要的高K材料的形成。优选的实施方案包括在高K材料层上形成一层材料，蚀刻该材料层以暴露一部分高K材料，进行CDE（化学下游蚀刻）去除在蚀刻和蚀刻高K材料层与材料层的剩余部分对准。剩余材料的去除导致高K材料的可预测的修整，使得半导体器件具有可预测和一致的性能，如果高K材料具有不可预测的尺寸，则这是不可能的。

74. 发明申请

US20070052113A1 Alignment marks for polarized light lithography and method for use thereof 有权
标题翻译：偏光光刻对准标记及其使用方法
公开(公告)号：US20070052113A1
公开(公告)日：2007-03-08
申请号：US11221202
申请日：2005-09-07
申请人： Sajan Marokkey , Chandrasekhar Sarma , Alois Gutmann
发明人： Sajan Marokkey , Chandrasekhar Sarma , Alois Gutmann
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality of elements comprised of a second component type, wherein the second component type has a second polarization, wherein the first polarization and the second polarization are orthogonal, wherein adjacent elements are of different component types. The alignment marks can be used in an intensity based or a diffraction based alignment process.
摘要翻译：用偏光光刻技术集成电路制造的标记和方法。优选实施例包括由第一部件类型构成的第一多个元件，其中第一元件类型具有第一偏振，第二元件类型具有第二元件类型，其中第二元件类型具有第二偏振，其中第一极化和第二极化是正交的，其中相邻元件是不同的组件类型。对准标记可以用于基于强度或基于衍射的对准过程。

75. 发明授权

US06521542B1 Method for forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06521542B1
公开(公告)日：2003-02-18
申请号：US09593739
申请日：2000-06-14
申请人： Mike Armacost , Bruno Spuler , Gabriela Brase , Alois Gutmann
发明人： Mike Armacost , Bruno Spuler , Gabriela Brase , Alois Gutmann
IPC分类号： H01L21302
CPC分类号： H01L21/76808
摘要： A method is provided for forming a step in a layer of material. The method includes forming the layer over a substrate. A cavity is formed in a portion of an upper surface of the layer. The formed cavity is filled with a filler material to provide a substantially planar surface over the substrate. A photoresist layer is formed over the substantially planar surface over the substrate. An aperture is formed in the photoresist layer in registration with the formed cavity. The aperture exposes a portion of the filler material. The exposed portion of the filler material is removed along with a contiguous portion of the layer to form the step in the indentation. The cavity may be either a trench or a via. A “Trench First” approach and a “Via First” approach are described.
摘要翻译：提供了一种用于在材料层中形成台阶的方法。该方法包括在衬底上形成该层。在该层的上表面的一部分中形成空腔。形成的空腔填充有填充材料，以在基底上提供基本平坦的表面。光致抗蚀剂层形成在衬底上的基本平坦的表面上。光致抗蚀剂层中形成有与形成的空腔对准的孔。孔径暴露了填充材料的一部分。填充材料的暴露部分与层的连续部分一起被去除以形成凹陷中的台阶。空腔可以是沟槽或通孔。描述了“首先采取沟通”方式和“首选”方式。

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