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71. 发明申请

US20080203468A1 FinFET with Reduced Gate to Fin Overlay Sensitivity 有权
标题翻译： FinFET具有降低栅极到Fin覆盖灵敏度
公开(公告)号：US20080203468A1
公开(公告)日：2008-08-28
申请号：US11680221
申请日：2007-02-28
申请人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack Allan Mandelman , John Edward Sheets
发明人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack Allan Mandelman , John Edward Sheets
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/785 , H01L29/045 , H01L29/66818
摘要： Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.
摘要翻译：本发明的实施例提供了Fin场效应晶体管（FinFET）中的相对均匀的宽度鳍片及其形成方法。翅片结构可以形成为使翅片结构的侧壁部分的表面垂直于第一结晶方向。翅片结构端部的锥形区域可以垂直于第二晶体方向。可以对翅片结构进行晶体依赖蚀刻。晶体依赖蚀刻可以相对较快地从第二晶体方向垂直于翅片的部分去除材料，从而形成相对均匀的宽度鳍片结构。

72. 发明授权

US07396762B2 Interconnect structures with linear repair layers and methods for forming such interconnection structures 有权
标题翻译：具有线性修复层的互连结构和用于形成这种互连结构的方法
公开(公告)号：US07396762B2
公开(公告)日：2008-07-08
申请号：US11468392
申请日：2006-08-30
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译：互连结构包括在绝缘层中形成在粗糙化介电材料上的衬垫中桥接破裂的共形衬里修复层以及形成这种互连结构的方法。保形衬里修复层由诸如含钴材料的导电材料形成。保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。

73. 发明申请

US20080146006A1 CRYSTAL IMPRINTING METHODS FOR FABRICATING SUBSTRATES WITH THIN ACTIVE SILICON LAYERS 有权
标题翻译：用薄膜活性硅层制作基板的水晶印刷方法
公开(公告)号：US20080146006A1
公开(公告)日：2008-06-19
申请号：US12040028
申请日：2008-02-29
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/20
CPC分类号： H01L29/045 , H01L21/84 , H01L27/1203
摘要： Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.
摘要翻译：通过晶体压印或镶嵌法在绝缘基板上形成由活性硅层薄的特征的半导体结构的方法。所述方法包括图案化绝缘层以限定多个孔，用非晶硅填充图案化绝缘层中的孔以限定多个非晶硅特征，以及重新生长非晶硅特征以限定薄的有源硅层，的再生硅特征。可以重新生长非晶硅特征，使得数量具有第一晶体取向，而另一数目具有不同的第二晶体取向。

74. 发明申请

US20080116582A1 Interconnect Structures with Improved Electromigration Resistance and Methods for Forming Such Interconnect Structures 有权
标题翻译：具有改进的电迁移电阻的互连结构和形成这种互连结构的方法
公开(公告)号：US20080116582A1
公开(公告)日：2008-05-22
申请号：US11562550
申请日：2006-11-22
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
IPC分类号： H01L23/535 , H01L21/768
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76885
摘要： Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the top surface and a substrate. An opening, such as a trench, has sidewalls extending from the top surface of the insulating layer toward the bottom surface and is at least partially filled by a conductive feature. A capping layer is disposed on at least a top surface of the conductive feature. A conductive liner layer is disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer has sidewall portions projecting above the top surface of the insulating layer adjacent to the sidewalls of the opening.
摘要翻译：互连结构包括与至少相邻绝缘层非平面的衬里层和在绝缘层中嵌入的导电特征上的至少一个覆盖层。互连结构包括具有上表面和顶表面与基底之间的底表面的电介质材料的绝缘层。诸如沟槽的开口具有从绝缘层的顶表面朝向底表面延伸并且至少部分地被导电特征填充的侧壁。覆盖层设置在导电特征的至少顶表面上。导电衬垫层至少沿着开口的侧壁设置在绝缘层和导电特征之间。导电衬垫层具有在与开口的侧壁相邻的绝缘层的顶表面上方突出的侧壁部分。

75. 发明授权

US07265696B2 Methods and apparatus for testing an integrated circuit 失效
公开(公告)号：US07265696B2
公开(公告)日：2007-09-04
申请号：US11272589
申请日：2005-11-10
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , Joseph O. Marsh , Steven J. Zier
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , Joseph O. Marsh , Steven J. Zier
IPC分类号： H03M1/10
CPC分类号： H03M1/1076
摘要： In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to test the analog circuit at a wafer level so as to detect a defect in one or more components of the analog circuit. Numerous other aspects are provided.

76. 发明授权

US06352882B1 Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation 有权
标题翻译：绝缘体上硅结构，用于静电放电保护和改善散热
公开(公告)号：US06352882B1
公开(公告)日：2002-03-05
申请号：US09624834
申请日：2000-07-25
申请人： Fariborz Assaderaghi , Louis Lu-Chen Hsu , Jack Allan Mandelman
发明人： Fariborz Assaderaghi , Louis Lu-Chen Hsu , Jack Allan Mandelman
IPC分类号： H01L2100
CPC分类号： H01L27/0266 , H01L21/84 , H01L23/3677 , H01L27/0255 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Doped polysilicon plugs are formed in contact with MOSFET device regions and passing through the buried oxide region into the opposite type silicon substrate of an SOI structure. The polysilicon plugs are in contact with the sources and drains of the MOSFET devices to provide paths for dissipating positive and negative ESD stresses. In addition, the polysilicon plugs provide a thermal dissipation pathway for directing heat away from the circuitry, and provide a diode for the structure.
摘要翻译：掺杂的多晶硅插塞形成为与MOSFET器件区域接触并且通过掩埋氧化物区域进入SOI结构的相对的硅衬底。多晶硅插塞与MOSFET器件的源极和漏极接触，以提供消除正和负ESD应力的路径。此外，多晶硅插头提供用于将热导向电路的散热路径，并为该结构提供二极管。

77. 发明授权

US6121661A Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation 失效
公开(公告)号：US6121661A
公开(公告)日：2000-09-19
申请号：US822440
申请日：1997-03-21
申请人： Fariborz Assaderaghi , Louis Lu-Chen Hsu , Jack Allan Mandelman
发明人： Fariborz Assaderaghi , Louis Lu-Chen Hsu , Jack Allan Mandelman
IPC分类号： H01L21/84 , H01L23/367 , H01L27/02 , H01L27/12 , H01L23/62 , H01L27/01 , H01L29/861
CPC分类号： H01L27/0266 , H01L21/84 , H01L23/3677 , H01L27/0255 , H01L27/1203 , H01L2924/0002
摘要： Doped polysilicon plugs are formed in contact with MOSFET device regions and passing through the buried oxide region into the opposite type silicon substrate of an SOI structure. The polysilicon plugs are in contact with the sources and drains of the MOSFET devices to provide paths for dissipating positive and negative ESD stresses. In addition, the polysilicon plugs provide a thermal dissipation pathway for directing heat away from the circuitry, and provide a diode for the structure.

78. 发明授权

US5930178A Bitline voltage stabilization device and method 失效
标题翻译：位线稳压装置及方法
公开(公告)号：US5930178A
公开(公告)日：1999-07-27
申请号：US971494
申请日：1997-11-17
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , Matthew Robert Wordeman
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , Matthew Robert Wordeman
IPC分类号： G11C7/12 , G11C11/4094 , G11C16/04
CPC分类号： G11C11/4094 , G11C7/12
摘要： A voltage control circuit for maintaining voltage levels on a pair of bitlines at a desirable above ground voltage is disclosed herein. In an exemplary embodiment, a semiconductor storage device includes a plurality of pairs of bitlines; a p-type field effect transistor multiplexer (PMUX) connecting each bitline of the pair to a sense amplifier; and a clamping circuit which prevents voltage levels on the bitlines from dwelling below a predetermined minimum voltage level. A method is also disclosed herein in which voltage levels on a pair of bitlines are maintained at a desirable above ground voltage level by connecting each bitline of a pair to a sense amplifier through a p-type field effect transistor multiplexer (PMUX); and clamping each bitline to prevent the voltage level thereon from dwelling below a predetermined minimum voltage level.
摘要翻译：本文公开了一种用于在期望的地面电压下保持一对位线上的电压电平的电压控制电路。在示例性实施例中，半导体存储装置包括多对位线; 将该对的每个位线连接到读出放大器的p型场效应晶体管多路复用器（PMUX）; 以及钳位电路，其防止位线上的电压水平低于预定的最小电压电平。本文还公开了一种方法，其中一对位线上的电压电平通过p型场效应晶体管多路复用器（PMUX）将一对的每个位线连接到读出放大器而保持在理想的接地电压电平; 并夹紧每个位线以防止其上的电压电平低于预定的最小电压电平。

79. 发明授权

US07879660B2 Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权
标题翻译：将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法
公开(公告)号：US07879660B2
公开(公告)日：2011-02-01
申请号：US11927780
申请日：2007-10-30
申请人： Roger Allen Booth, Jr. , Jack Allan Mandelman , William Robert Tonti
发明人： Roger Allen Booth, Jr. , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译：通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷并且至少部分地用介电材料填充凹部。

80. 发明授权

US07611931B2 Semiconductor structures with body contacts and fabrication methods thereof 有权
标题翻译：具有身体接触的半导体结构及其制造方法
公开(公告)号：US07611931B2
公开(公告)日：2009-11-03
申请号：US11928135
申请日：2007-10-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Allan Mandelman
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Allan Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/0218 , H01L27/10841 , H01L27/10864 , H01L27/10891
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.
摘要翻译：一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触晶圆。半导体本体包括用于垂直存储单元之一的存取装置的通道区域。延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。

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