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71. 发明授权

US5615055A Dual-mode digital signal recording and/or reproducing apparatus 失效
标题翻译：双模式数字信号记录和/或再现装置
公开(公告)号：US5615055A
公开(公告)日：1997-03-25
申请号：US383710
申请日：1995-02-01
申请人： Shinichi Fukuda , Akio Tanaka , Kentaro Odaka
发明人： Shinichi Fukuda , Akio Tanaka , Kentaro Odaka
IPC分类号： G11B20/00 , G11B20/10 , G11B27/032 , G11B5/00
CPC分类号： G11B20/10527 , G11B20/00007 , G11B27/032 , G11B2220/90 , G11B2220/913
摘要： A digital audio tape recorder for processing input signals in a predetermined manner and for digitally recording the processed signals on a recording medium or reproducing digital signals recorded on the recording medium by a rotary head has a time base compressing unit and a time base expanding unit for time base compressing signals supplied to the rotary head or time base expanding signals reproduced from the rotary head for recording and reproducing data at a high transmission rate on or from the recording medium. Time base compression/expansion and the rotation of the rotary head at a number of revolutions in conformity to the high transmission rate are achieved.
摘要翻译：一种用于以预定方式处理输入信号并将数字记录在记录介质上的数字音频磁带录像机或通过旋转磁头重放记录在记录介质上的数字信号，具有时基压缩单元和时基扩展单元，提供给旋转磁头的时基压缩信号或从旋转磁头重放的时基扩展信号，用于以高传输速率在记录介质上记录和再现数据。实现了时基压缩/扩展以及旋转头的转动，转数符合高传输速率。

72. 发明授权

US5343215A AC refresh type plasma display system uniformly illuminating pixels 失效
标题翻译：交流刷新式等离子显示系统均匀照明像素
公开(公告)号：US5343215A
公开(公告)日：1994-08-30
申请号：US917410
申请日：1992-07-23
申请人： Akio Tanaka
发明人： Akio Tanaka
IPC分类号： G09G3/288 , G09G3/20 , G09G3/296 , G09G3/28
CPC分类号： G09G3/2946 , G09G2360/16 , G09G3/297
摘要： An AC refresh type plasma display panel system drives scanning electrodes in sequential manner with a first address pulse signal and a hold pulse signal and data electrodes in selective manner with a second address pulse signal, and forms visual images on a matrix of pixels addressable with the scanning electrodes and the data electrodes, wherein the frequency of the hold pulse signal is variable with the number of illuminated pixels on each scanning line so that the luminance of each pixel is kept constant.
摘要翻译： AC刷新型等离子体显示面板系统以第一寻址脉冲信号和保持脉冲信号以及数据电极以第二寻址脉冲信号的选择性方式顺序地驱动扫描电极，并且在可以与扫描电极和数据电极，其中保持脉冲信号的频率随着每个扫描线上的照明像素的数量而变化，使得每个像素的亮度保持恒定。

73. 发明授权

US5260683A Tire pressure detecting apparatus for vehicle 失效
标题翻译：车辆用轮胎压力检测装置
公开(公告)号：US5260683A
公开(公告)日：1993-11-09
申请号：US680667
申请日：1991-04-05
申请人： Akio Tanaka , Masaru Suzuki , Hideki Miyazawa , Kazuma Matsui , Tetsuya Nagata , Yutaka Ohasi , Yoshihisa Nakano
发明人： Akio Tanaka , Masaru Suzuki , Hideki Miyazawa , Kazuma Matsui , Tetsuya Nagata , Yutaka Ohasi , Yoshihisa Nakano
IPC分类号： B60C23/04 , B60C23/20 , B60C23/00
CPC分类号： B60C23/20 , B60C23/0428 , B60C23/0498
摘要： A tire pressure detecting portion includes a housing, provided within the tire, within which a piezoelectric element is provided so as to be deformed by the tire pressure. The capacitance of said piezoelectric element is changed in accordance with its deformation. The piezoelectric element is electrically connected with a first coil diposed within said tire. The first coil is electromagnetically coupled with an excitation coil and a receiving coil, both of which are provided in the vehicle. The excitation coil provides an excitation voltage whole frequency is changed within a predetermined range including a resonant frequency. When the received voltage has the resonant frequency, a correspondinq tire pressure is determined based on a data map showing the relationship between said resonant frequency and the tire pressure.

74. 发明授权

US5231382A Plasma display apparatus 失效
标题翻译：等离子显示装置
公开(公告)号：US5231382A
公开(公告)日：1993-07-27
申请号：US662006
申请日：1991-02-27
申请人： Akio Tanaka
发明人： Akio Tanaka
IPC分类号： G09G3/288 , G09G3/20 , G09G3/291 , G09G3/292 , G09G3/294
CPC分类号： G09G3/2944 , G09G3/297
摘要： The invention provides voltage potential differences for selectively discharging cells in a plasma display device, with greater brightness and reduced power consumption. The driving pulses applied to either selected cells or non-selected cells during one scanning cycle includes a high frequency hold mode period after a low frequency address mode period. During the hold mode period, a duty factor of its pulse train is selected to be smaller than that of the address mode period. Particularly, the pulse width of the pulse train in the hold mode period is shorter than an interval of pulses thereof. In other words, the duty factor of the hold mode period is selected to be less than 1/2 to decrease the voltage causing an erroneous discharge. In another embodiment, to improve brightness, the duration of hold mode is, extended to cover one more scanning cycle.
摘要翻译：本发明提供了用于在等离子体显示装置中选择性地放电电池的电压电位差，具有更大的亮度和降低的功耗。在一个扫描周期期间施加到所选择的单元或非选择单元的驱动脉冲包括在低频地址模式周期之后的高频保持模式周期。在保持模式期间，选择其脉冲序列的占空系数小于地址模式周期的占空系数。特别地，保持模式周期中的脉冲串的脉冲宽度比其脉冲间隔短。换句话说，保持模式周期的占空比被选择为小于1/2以减小导致错误放电的电压。在另一个实施例中，为了提高亮度，保持模式的持续时间延长到覆盖一个以上的扫描周期。

75. 发明授权

US4967246A Structure of insulated gate bipolar transistors 失效
标题翻译：绝缘栅双极晶体管的结构
公开(公告)号：US4967246A
公开(公告)日：1990-10-30
申请号：US261708
申请日：1988-10-24
申请人： Akio Tanaka
发明人： Akio Tanaka
IPC分类号： H01L21/8222 , H01L21/331 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/07 , H01L29/73 , H01L29/732 , H01L29/739 , H01L29/78
CPC分类号： H01L27/0716 , H01L29/7393
摘要： There is disclosed the structure of an insulated gate bipolar transistor which is formed in an n-type island formed in a p-type substrate and comprises an n-type well and a p-type base in the island in a spacing relationship, n-type and p-type source regions in the n-type well, an n-type drain in the base and an extension projecting from the base, and an integrated circuit is fabricated on the single substrate by virtue of the junction isolations.
摘要翻译：公开了一种绝缘栅双极晶体管的结构，该绝缘栅双极晶体管形成在形成于p型衬底中的n型岛中，并且在岛中具有间隔关系的n型阱和p型基极， n型阱中的n型漏极和p型源极区，基极中的n型漏极和从基极突出的延伸，并且通过结隔离在单个衬底上制造集成电路。

76. 发明授权

US4874164A Personal computer apparatus for block transfer of bit-mapped image data 失效
标题翻译：用于块映射图像数据的块传送的个人计算机装置
公开(公告)号：US4874164A
公开(公告)日：1989-10-17
申请号：US886796
申请日：1986-07-18
申请人： Jay G. Miner , Dave Dean , Joseph C. Decuir , Ronald H. Nicholson , Akio Tanaka
发明人： Jay G. Miner , Dave Dean , Joseph C. Decuir , Ronald H. Nicholson , Akio Tanaka
IPC分类号： G06F3/153 , A63F13/00 , G09G5/00 , G09G5/02 , G09G5/24 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/395
CPC分类号： G09G5/024 , A63F13/00 , A63F13/40 , G09G5/24 , G09G5/363 , G09G5/39 , A63F2300/203 , G09G2360/127 , G09G5/346
摘要： A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transfer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the value for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.
摘要翻译：使用位图显示存储器组织和位平面寻址为视频显示提供数据的计算机。提供了两个位平面背景和八个可重复使用且易于移动的精灵的独立控制。额外的逻辑允许在每个位平面背景和精灵中的数据之间动态可控的对象间优先级和碰撞检测。协处理器为寄存器中的数据提供视频波束同步更改，为主处理器释放通用计算任务。提供块图像传输以将大块中的数据从一个存储器位置快速复制到另一个存储器位置。在保持和修改模式下，颜色输出电路保持先前显示的像素的值，而位平面数据修改这些值，允许同时显示大量增加的颜色数量。

77. 外观设计

USD290697S Speaker 失效
公开(公告)号：USD290697S
公开(公告)日：1987-07-07
申请号：US663621
申请日：1984-10-22
申请人： Akio Tanaka , Akira Katsuno
设计人： Akio Tanaka , Akira Katsuno

78. 发明授权

US4275806A Coin sorting machine 失效
标题翻译：硬币分拣机
公开(公告)号：US4275806A
公开(公告)日：1981-06-30
申请号：US913161
申请日：1978-06-06
申请人： Akio Tanaka , Yoshihisa Nakajima , Shinji Yokomori
发明人： Akio Tanaka , Yoshihisa Nakajima , Shinji Yokomori
IPC分类号： G07D5/08 , G07D3/00 , G07D3/14 , G07D5/02 , G07D11/00
CPC分类号： G07D3/14 , G07D5/02 , G07D5/08
摘要： In a coin sorting machine of the type wherein a sorting coil for detecting the characteristics of a coin inserted into the machine is provided along a coin passage and the output signal of the coil is varied to thereby determine whether the inserted coin is true or false when the coin passes by the sorting coil, a coin sorting period is determined by detecting the position of the inserted coin rolling along the coin passage, and the inserted coin is sorted depending on whether or not a predetermined sorting signal is outputted during the coin sorting period.
摘要翻译：在这种类型的硬币分选机中，沿着硬币通道设置用于检测插入到机器中的硬币的特性的分类线圈，并且线圈的输出信号被改变，从而确定所插入的硬币是否是真或假，硬币通过分类线圈，通过检测插入的硬币沿着硬币通道滚动的位置来确定硬币分选周期，并且根据在硬币分类期间是否输出预定的分类信号来分选插入的硬币。

79. 发明授权

US4268903A Stack control system and method for data processor 失效
标题翻译：数据处理器的堆栈控制系统和方法
公开(公告)号：US4268903A
公开(公告)日：1981-05-19
申请号：US964089
申请日：1978-11-27
申请人： Yusaku Miki , Hidemi Yamamoto , Yuichi Kimihira , Akio Tanaka
发明人： Yusaku Miki , Hidemi Yamamoto , Yuichi Kimihira , Akio Tanaka
IPC分类号： G06F9/34 , G06F7/78 , G06F9/42 , G06F13/06
CPC分类号： G06F7/785 , G06F9/4426
摘要： A data processor having a stack area with a desirable variable size formed on a desirable area of a main memory unit in accordance with a direction by a user program, is provided with a stack control register group for controlling the stack area. A stack upper address register in the stack control register group holds the upper address specified on the stack area. The stack lower address register holds the lower limit address specified. A control stack pointer register holds the start address of a control stack area formed on the stack area for storing the number of a register specified by a user program and the contents thereof. A data stack pointer register holds the start address of the data stack area which is formed on said stack area and used by the user program.
摘要翻译：具有根据用户程序的方向形成在主存储单元的期望区域上具有期望可变大小的堆栈区域的数据处理器具有用于控制堆栈区域的堆栈控制寄存器组。堆栈控制寄存器组中的堆栈上地址寄存器保存堆栈区域中指定的高位地址。堆栈下地址寄存器保存指定的下限地址。控制堆栈指针寄存器保存形成在堆栈区域上的控制堆栈区域的起始地址，用于存储由用户程序指定的寄存器的数量及其内容。数据堆栈指针寄存器保存形成在所述堆栈区域上并由用户程序使用的数据堆栈区域的起始地址。

80. 发明授权

US4257435A Mischief preventing device for a coin sorting machine 失效
标题翻译：用于硬币分拣机的防病装置
公开(公告)号：US4257435A
公开(公告)日：1981-03-24
申请号：US913165
申请日：1978-06-06
申请人： Akio Tanaka , Yoshihisa Nakajima , Shinji Yokomori
发明人： Akio Tanaka , Yoshihisa Nakajima , Shinji Yokomori
IPC分类号： G07D5/00 , G07D3/14 , G07D3/16 , G07F3/02
CPC分类号： G07D3/14 , G07D3/16
摘要： Erroneous counting of both false coins and real coins tied to a string is prevented by providing a two stage counter with a gate in the middle. The first stage determines whether the coin is real and, if real, what its value is. If the coin is real a gate is opened and the coin passes a detector which shuts the gate while simultaneously counting the coin value from the first stage.
摘要翻译：通过在中间设置带有门的两级计数器来防止错误计数绑在字符串上的伪币和真实硬币。第一阶段确定硬币是否是真实的，如果是真实的，它的价值是什么。如果硬币是真实的，门打开，硬币通过一个关闭门的检测器，同时从第一阶段计数硬币值。

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