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71. 发明申请

US20090052254A1 Non-Volatile Semiconductor Memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20090052254A1
公开(公告)日：2009-02-26
申请号：US12257828
申请日：2008-10-24
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
摘要翻译：非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中在预定的阈值电平范围内。在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于要存储在其中一个存储单元中的一位二电平数据。

72. 发明授权

US07330372B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07330372B2
公开(公告)日：2008-02-12
申请号：US11366110
申请日：2006-03-01
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/04
CPC分类号： G11C16/105 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/26 , G11C2216/14
摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.
摘要翻译：一种非易失性半导体存储器件包括其中布置有电可重写非易失性存储器单元的存储单元阵列，用于执行存储单元阵列的存储单元选择的地址选择器电路，布置成执行数据读取的数据读/写电路的存储单元阵列和写入存储单元阵列的数据;以及控制电路，用于执行一系列复制写入操作，使得从数据读/写电路到芯片外部的数据输出操作和从数据读/写电路到存储单元阵列的数据写入操作彼此重叠，复制写操作包括将存储单元阵列的特定地址处的数据读入数据读/写电路，输出保持在读/写电路到芯片外部，并将写入数据写入存储单元阵列的另一个地址，写数据是保存在数据读/写中的读数据的修改版本 ite电路在芯片外部外部创建。

73. 发明申请

US20060104112A1 Non-volatile semiconductor memory 有权
公开(公告)号：US20060104112A1
公开(公告)日：2006-05-18
申请号：US11318524
申请日：2005-12-28
申请人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

74. 发明授权

US06999344B2 Non-volatile semiconductor memory device and electric device with the same 失效
标题翻译：非易失性半导体存储器件和电器件相同
公开(公告)号：US06999344B2
公开(公告)日：2006-02-14
申请号：US11077640
申请日：2005-03-11
申请人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Kenichi Imamiya
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/28 , G11C16/3418 , G11C2211/5643
摘要： A non-volatile semiconductor memory device includes: a memory cell array in which electrically rewritable floating gate type memory cells are arranged; and a plurality of sense amplifier circuits configured to read data from the memory cell array, wherein each the sense amplifier circuit is configured to sense cell data of a first memory cell selected from the memory cell array under a read condition determined in correspondence with cell data of a second memory cell adjacent to the first memory cell and written after the first memory cell.
摘要翻译：非挥发性半导体存储器件包括：其中布置有电可重写浮动型存储单元的存储单元阵列; 以及多个读出放大器电路，被配置为从存储单元阵列读取数据，其中每个读出放大器电路被配置为在与单元数据相对应的读取条件下感测从存储单元阵列中选择的第一存储单元的单元数据与第一存储器单元相邻并且写在第一存储单元之后的第二存储器单元。

75. 发明申请

US20050157560A1 Non-volatile semiconductor memory device 有权
公开(公告)号：US20050157560A1
公开(公告)日：2005-07-21
申请号：US11077046
申请日：2005-03-09
申请人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
发明人： Koji Hosono , Kenichi Imamiya , Hiroshi Nakamura
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/26 , G11C11/34
CPC分类号： G11C16/105 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/26 , G11C2216/14
摘要： A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

76. 发明授权

US06597602B2 Semiconductor memory device 有权
公开(公告)号：US06597602B2
公开(公告)日：2003-07-22
申请号：US09956937
申请日：2001-09-21
申请人： Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
发明人： Kenichi Imamiya , Hiroshi Nakamura , Koji Hosono
IPC分类号： G11C1604
CPC分类号： G11C16/22
摘要： A semiconductor memory device is provided which includes a rewrite-inhibited region for individual certification. Non-volatile memory elements constituting a memory cell array are used instead of a conventionally used fuse element to form the rewrite-inhibited region for individual certification. A voltage at high level is applied to a pad formed on a chip with a probe before the chip is sealed in a package to set the non-volatile memory elements in the rewrite-inhibited region to a writable state. After data for individual certification is written thereto, the chip is sealed in a package to disable electrical connection from outside to the pad set to a voltage at low level with a pull-down resistor.

77. 发明授权

US06278639B1 Booster circuit having booster cell sections connected in parallel, voltage generating circuit and semiconductor memory which use such booster circuit 失效
标题翻译：具有并联连接的升压电池部分的升压电路，电压产生电路和使用这种升压电路的半导体存储器
公开(公告)号：US06278639B1
公开(公告)日：2001-08-21
申请号：US09392127
申请日：1999-09-08
申请人： Koji Hosono , Hiroshi Nakamura , Tamio Ikehashi , Kazushige Kanda , Ken Takeuchi , Kenichi Imamiya
发明人： Koji Hosono , Hiroshi Nakamura , Tamio Ikehashi , Kazushige Kanda , Ken Takeuchi , Kenichi Imamiya
IPC分类号： G11C700
CPC分类号： G11C5/145
摘要： The booster circuit of the present invention includes a first booster cell section in which one or more booster cells are connected in series, and a second booster cell section having an end which is connected to the first booster cell section, in which a plurality of booster cell groups each containing one or more booster cells connected in series, are connected to each other in parallel.
摘要翻译：本发明的升压电路包括其中一个或多个升压电池串联连接的第一升压电池部分和具有连接到第一升压电池部分的端部的第二升压电池部分，其中多个增压器每个包含串联连接的一个或多个升压电池的电池组彼此并联连接。

78. 发明授权

US07286400B2 Non-volatile semiconductor memory device with pass/fail detection circuit 有权
标题翻译：具有通过/失败检测电路的非易失性半导体存储器件
公开(公告)号：US07286400B2
公开(公告)日：2007-10-23
申请号：US11219756
申请日：2005-09-07
申请人： Masatsugu Kojima , Koji Hosono , Koichi Kawai
发明人： Masatsugu Kojima , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to read data of the memory cell array; and a pass/fail detection circuit configured to detect write or erase completion based on verify-read data stored in the sense amplifier circuit in data write or erase mode, wherein the pass/fail detection circuit comprises a data latch, into which a defective column isolation data is writable in accordance with a command input.
摘要翻译：非挥发性半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元;读出放大器电路，被配置为读取存储单元阵列的数据; 以及通过/失败检测电路，被配置为基于在数据写入或擦除模式中存储在读出放大器电路中的验证读取数据来检测写入或擦除完成，其中，该通过/失败检测电路包括数据锁存器，缺陷列隔离数据可根据命令输入进行写入。

79. 发明申请

US20060050564A1 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20060050564A1
公开(公告)日：2006-03-09
申请号：US11219756
申请日：2005-09-07
申请人： Masatsugu Kojima , Koji Hosono , Koichi Kawai
发明人： Masatsugu Kojima , Koji Hosono , Koichi Kawai
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged: a sense amplifier circuit configured to read data of the memory cell array; and a pass/fail detection circuit configured to detect write or erase completion based on verify-read data stored in the sense amplifier circuit in data write or erase mode, wherein the pass/fall detection circuit comprises a data latch, into which a defective column isolation data is writable in accordance with a command input.
摘要翻译：非挥发性半导体存储器件包括：存储单元阵列，其中布置有电可重写和非易失性存储单元;读出放大器电路，被配置为读取存储单元阵列的数据; 以及通过/失败检测电路，被配置为基于在数据写入或擦除模式中存储在读出放大器电路中的验证读取数据来检测写入或擦除完成，其中，通过/下降检测电路包括数据锁存器，缺陷列隔离数据可根据命令输入进行写入。

80. 发明授权

US08724391B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08724391B2
公开(公告)日：2014-05-13
申请号：US13423610
申请日：2012-03-19
申请人： Dai Nakamura , Koji Hosono , Hidehiro Shiga
发明人： Dai Nakamura , Koji Hosono , Hidehiro Shiga
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/16 , G11C16/28
摘要： According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.
摘要翻译：根据一个实施例，半导体存储器件包括第一和第二选择晶体管，存储单元，驱动电路，第一传输晶体管和检测电路。存储单元堆叠在半导体衬底之上。驱动电路输出第一电压。第一传输晶体管将第一电压转移到相关联的字线并选择栅极线。在数据擦除中，检测电路检测施加到位线和/或源极线的第二电压，并根据检测结果生成标志。驱动电路响应于标志来改变第一电压的值以切断第一转移晶体管。

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