专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20080144811A1 Method for Simultaneous Modular Exponentiations 有权
标题翻译：同时模块化指标的方法
公开(公告)号：US20080144811A1
公开(公告)日：2008-06-19
申请号：US11610919
申请日：2006-12-14
申请人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
IPC分类号： H04L9/30
CPC分类号： G06F7/723 , H04L9/302
摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的方法。该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q））。该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数第二余数（xq）升至第二素数（q）的第二私钥号（d2）。该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

72. 发明申请

US20140156790A1 BITSTREAM PROCESSING USING COALESCED BUFFERS AND DELAYED MATCHING AND ENHANCED MEMORY WRITES 有权
标题翻译：使用加密缓存和延迟匹配和增强存储器写入的BITSTREAM处理
公开(公告)号：US20140156790A1
公开(公告)日：2014-06-05
申请号：US13994129
申请日：2011-12-23
申请人： Vinodh Gopal , Jim D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghail , Deniz Karakoyunlu , Erdinc Ozturk , Martin Dixon , Kahraman Akdemir
发明人： Vinodh Gopal , Jim D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghail , Deniz Karakoyunlu , Erdinc Ozturk , Martin Dixon , Kahraman Akdemir
IPC分类号： H04L29/06
CPC分类号： H04L65/607 , H03M7/30 , H03M7/3086 , H04L65/608 , H04L69/04 , H04L69/22 , H04W28/06
摘要： Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.
摘要翻译：用于处理比特流和字节流的方法和装置。根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。如果这样做，令牌的len值通过使用合并缓冲区来添加。在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器）检测位累加器是满或接近满的操作。

73. 发明授权

US07925011B2 Method for simultaneous modular exponentiations 有权
标题翻译：同时采用模幂分析的方法
公开(公告)号：US07925011B2
公开(公告)日：2011-04-12
申请号：US11610919
申请日：2006-12-14
申请人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuksel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuksel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
IPC分类号： H04L9/00
CPC分类号： G06F7/723 , H04L9/302
摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder (v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number (q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的方法。该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q））。该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数第二余数（xq）升至第二素数（q）的第二私钥号（d2）。该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

74. 发明授权

US08953785B2 Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor 有权
标题翻译： 128位处理器上的SKEIN256 SHA3算法指令集
公开(公告)号：US08953785B2
公开(公告)日：2015-02-10
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

75. 发明申请

US20140093068A1 INSTRUCTION SET FOR SKEIN256 SHA3 ALGORITHM ON A 128-BIT PROCESSOR 有权
标题翻译： 128位处理器的SKEIN256 SHA3算法指令集
公开(公告)号：US20140093068A1
公开(公告)日：2014-04-03
申请号：US13631143
申请日：2012-09-28
申请人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
发明人： Gilbert M. Wolrich , Kirk S. Yap , Vinodh Gopal
IPC分类号： H04L9/28
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30032 , G06F9/30036
摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.
摘要翻译：根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联具有存储多个偶数字的第二存储位置和第三操作数。处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

76. 发明申请

US20170091120A1 Securing Writes to Memory Modules Having Memory Controllers 审中-公开
公开(公告)号：US20170091120A1
公开(公告)日：2017-03-30
申请号：US14865675
申请日：2015-09-25
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： G06F12/14 , G06F11/16 , G06F11/32
CPC分类号： G06F12/1408 , G06F11/1608 , G06F11/327 , G06F13/00 , G06F21/575 , G06F21/79 , G06F2212/1052
摘要： A host central processing unit subsystem that writes information to external memory may provide policy to the external memory. Then every time a write comes from the host subsystem, a memory controller within the memory may check the write against the policy stored in the memory and decide whether or not to implement the write.

77. 发明申请

US20140189368A1 INSTRUCTION AND LOGIC TO PROVIDE SIMD SECURE HASHING ROUND SLICE FUNCTIONALITY 有权
标题翻译：指示和逻辑提供SIMD安全冲击圆形功能
公开(公告)号：US20140189368A1
公开(公告)日：2014-07-03
申请号：US13731004
申请日：2012-12-29
申请人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap
发明人： Gilbert M. Wolrich , Vinodh Gopal , Kirk S. Yap
IPC分类号： G06F21/60
CPC分类号： H04L9/0643 , G06F9/30007 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G06F15/8007 , G06F21/602 , G06F21/64
摘要： Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.
摘要翻译：说明和逻辑提供SIMD安全散列圆切片功能。一些实施例包括处理器，包括：解码级，用于解码用于SIMD安全散列算法圆切片的指令，指定源数据操作数集合的指令，消息加常数操作数集合，安全散列的圆切片部分圆周运算，旋转设定部分旋转设定。处理器执行单元响应于解码的指令，在源数据操作数集合上执行循环迭代的安全散列圆切片集合，应用消息加常数操作数集合和旋转器集合，并且存储 SIMD目的寄存器中的指令。该指令的一个实施例将哈希循环类型指定为四个MD5循环类型之一。其他实施例可以通过立即操作数来指定散列循环类型，作为三种SHA-1轮型之一或SHA-2轮型。

78. 发明申请

US20170093823A1 Encrypting Observable Address Information 审中-公开
公开(公告)号：US20170093823A1
公开(公告)日：2017-03-30
申请号：US14865751
申请日：2015-09-25
申请人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
发明人： Vinodh Gopal , Gilbert M. Wolrich , Kirk S. Yap
IPC分类号： H04L29/06 , G06F12/14
CPC分类号： H04L63/061 , G06F12/1416 , G06F21/78 , G06F2212/1052 , H04L63/0442
摘要： Address information may be secured by sharing a key between a host central processing unit subsystem and an external memory. Information about how write addresses are modified may be exchanged between said subsystem and said memory. The write addresses for the same memory location are changed each time a write accesses the address.

79. 发明申请

US20170177404A1 HARDWARE ACCELERATORS AND METHODS FOR STATEFUL COMPRESSION AND DECOMPRESSION OPERATIONS 审中-公开
公开(公告)号：US20170177404A1
公开(公告)日：2017-06-22
申请号：US14975847
申请日：2015-12-20
申请人： Tracy G. Drysdale , James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , James T. Kukunas
发明人： Tracy G. Drysdale , James D. Guilford , Vinodh Gopal , Gilbert M. Wolrich , James T. Kukunas
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/466 , G06F9/5061 , G06F9/544 , G06F9/546 , G06F2209/509
摘要： Methods and apparatuses relating to stateful compression and decompression operations are described. In one embodiment, hardware processor includes a core to execute a thread and offload at least one of a compression and decompression thread, and a hardware compression and decompression accelerator to execute the at least one of the compression and decompression thread to consume input and generate output data, wherein the hardware compression and decompression accelerator is coupled to a plurality of input buffers to store the input data, a plurality of output buffers to store the output data, an input buffer descriptor array with an entry for each respective input buffer, an input buffer response descriptor array with a corresponding response entry for each respective input buffer, an output buffer descriptor array with an entry for each respective output buffer, and an output buffer response descriptor array with a corresponding response entry for each respective output buffer.

80. 发明授权

US09473168B1 Systems, methods, and apparatuses for compression using hardware and software 有权
标题翻译：使用硬件和软件进行压缩的系统，方法和装置
公开(公告)号：US09473168B1
公开(公告)日：2016-10-18
申请号：US14866746
申请日：2015-09-25
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Daniel F. Cutter
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Daniel F. Cutter
IPC分类号： H03M7/00 , H03M7/30
CPC分类号： H03M7/3082 , H03M7/3086 , H03M7/40
摘要： Detailed herein are embodiments of systems, methods, and apparatuses for compression using hardware and software. Embodiments include compressor hardware to operate on two streams with one of the streams being an offset of the other stream. Additionally, in some embodiments, the output of the compressor hardware is submitted to software for further processing.
摘要翻译：这里详细描述了使用硬件和软件进行压缩的系统，方法和装置的实施例。实施例包括在两个流之间操作的压缩器硬件，其中一个流是另一个流的偏移。另外，在一些实施例中，压缩机硬件的输出被提交给软件进行进一步的处理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式