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71. 发明申请

US20130069167A1 SRAM CELL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： SRAM单元及其制造方法
公开(公告)号：US20130069167A1
公开(公告)日：2013-03-21
申请号：US13509912
申请日：2011-11-21
申请人： Huilong Zhu , Qingqing Liang
发明人： Huilong Zhu , Qingqing Liang
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L21/823431 , H01L27/1104
摘要： A SRAM cell and a method for manufacturing the same are disclosed. In one embodiment, the SRAM cell may comprise: a semiconductor layer; and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the semiconductor layer, wherein the first FinFET comprises a first fin formed by patterning the semiconductor layer, the first fin having a first top surface and a first bottom surface, wherein the second FinFET comprises a second fin formed by patterning the semiconductor layer, the second fin having a second top surface and a second bottom surface, and wherein the first top surface is substantially flush with the second top surface, the first and second bottom surfaces abut against the semiconductor layer, and the height of the second fin is greater than the height of the first fin.
摘要翻译：公开了SRAM单元及其制造方法。在一个实施例中，SRAM单元可以包括：半导体层; 以及形成在所述半导体层上的第一Fin场效应晶体管（FinFET）和第二FinFET，其中所述第一FinFET包括通过对所述半导体层进行图案化而形成的第一鳍，所述第一鳍具有第一顶表面和第一底表面，其中第二FinFET包括通过图案化半导体层形成的第二鳍片，第二鳍片具有第二顶表面和第二底表面，并且其中第一顶表面基本上与第二顶表面齐平，第一和第二底表面邻接并且第二散热片的高度大于第一散热片的高度。

72. 发明申请

US20130009244A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130009244A1
公开(公告)日：2013-01-10
申请号：US13379444
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/42384 , H01L29/78648
摘要： The present application discloses an MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first insulation buried layer disposed on the semiconductor substrate; a back gate formed in a first semiconductor layer which is disposed on the first insulation buried layer; a second insulation buried layer disposed on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is disposed on the second insulation buried layer; a gate disposed on the second semiconductor layer; and electric connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoins the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions. The MOSFET, of any conductivity type, can have adjustable threshold voltage and reduced leakage current via the back gate between the source/drain regions by using the back gate in the form of a PNP junction or an NPN junction.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 设置在所述半导体基板上的第一绝缘埋层; 形成在第一绝缘掩埋层上的第一半导体层中形成的背栅; 设置在所述第一半导体层上的第二绝缘埋层; 源极/漏极区域，形成在第二绝缘掩埋层上的第二半导体层中; 设置在所述第二半导体层上的栅极; 以及与源极/漏极区域，栅极和背栅极的电连接，其中所述背栅极包括设置在所述源极/漏极区域下方的第一导电类型的第一后栅极区域和具有第二导电性的第二背栅极区域所述第一导电类型与所述第二导电类型相反，并且与所述第二导电类型的电连接包括与所述第二导电类型之一接触的导电通孔，第一个后门区域。任何导电类型的MOSFET可以通过使用PNP结或NPN结形式的背栅，通过源极/漏极区之间的背栅极具有可调节的阈值电压和减小的漏电流。

73. 发明申请

US20130001665A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130001665A1
公开(公告)日：2013-01-03
申请号：US13379433
申请日：2011-08-02
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/78648
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate.
摘要翻译：本公开公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘层和半导体层，所述埋入绝缘层设置在所述半导体基板上，半导体层设置在掩埋绝缘层上; 设置在半导体层上的栅极堆叠; 源极区域和漏极区域，嵌入在半导体层中并设置在栅极叠层的两侧; 以及嵌入所述半导体层并夹在所述源极区域和所述漏极区域之间的沟道区域，其中所述MOSFET还包括背栅极和反向掺杂区域，并且其中所述背栅极嵌入所述半导体衬底中，所述反掺杂区域设置在沟道区域下方并嵌入在后栅极中，并且背栅极具有与反相掺杂区域相反的掺杂型。 MOSFET可以通过改变背栅极的掺杂类型来调节阈值电压。

74. 发明申请

US20120326155A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120326155A1
公开(公告)日：2012-12-27
申请号：US13376247
申请日：2011-08-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/84 , H01L21/823828 , H01L21/823878 , H01L27/1203 , H01L29/4908 , H01L29/78603 , H01L29/78612
摘要： The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括：SOI衬底和形成在SOI衬底上的MOSFET，其中SOI衬底以自顶向下的方式包括SOI层，第一掩埋绝缘体层，埋入半导体层，第二掩埋绝缘体层和半导体衬底，所述掩埋半导体层包括背栅区，所述背栅区包括掺杂有第一极性的掺杂剂的所述掩埋半导体层的一部分; MOSFET包括栅极堆叠和源极/漏极区，栅极堆叠形成在SOI层上，并且源极/漏极区域形成在栅极堆叠的相对侧的SOI层中; 并且所述背栅区域包括反掺杂区域，所述反掺杂区域与所述栅叠层自对准并且包括第二极性的掺杂剂，并且所述第二极性与所述第一极性相反。本公开的实施例可以用于调整MOSFET的阈值电压。

75. 发明申请

US20120309139A1 METHOD FOR MANUFACTURING FIN FIELD-EFFECT TRANSISTOR 有权
标题翻译： FIN场效应晶体管的制造方法
公开(公告)号：US20120309139A1
公开(公告)日：2012-12-06
申请号：US13375976
申请日：2011-08-10
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795
摘要： An embodiment of the present invention discloses a method for manufacturing a FinFET, when a fin is formed, a dummy gate across the fin is formed on the fin, a source/drain opening is formed in both the cover layer and the first dielectric layer at both sides of the dummy gate, the source/drain opening is at both sides of the fin covered by the dummy gate and is an opening region surrounded by the cover layer and the first dielectric layer around it. In the formation of a source/drain region in the source/drain opening, stress is generated due to lattice mismatching, and applied to the channel due to the limitation by the source/drain opening in the first dielectric layer, thereby increasing the carrier mobility of the device, and improving the performance of the device.
摘要翻译：本发明的一个实施例公开了一种制造FinFET的方法，在翅片形成时，在翅片上形成跨鳍片的虚拟栅极，在覆盖层和第一电介质层中形成源极/漏极开口虚拟栅极的两侧，源极/漏极开口处于由虚拟栅极覆盖的鳍的两侧，并且是由覆盖层和围绕其的第一介电层包围的开口区域。在源极/漏极开口中的源极/漏极区域的形成中，由于晶格失配而产生应力，并且由于第一介电层中的源极/漏极开口的限制而施加到沟道，从而增加载流子迁移率的设备，并提高设备的性能。

76. 发明申请

US20120193798A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20120193798A1
公开(公告)日：2012-08-02
申请号：US13129321
申请日：2011-02-26
申请人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L23/48 , H01L23/482 , H01L21/768
CPC分类号： H01L23/53276 , H01L21/76807 , H01L21/76843 , H01L21/76846 , H01L21/76847 , H01L21/76877 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards.
摘要翻译：半导体器件结构及其制造方法技术领域本发明涉及半导体器件结构及其制造方法。该结构包括：其上形成有器件结构的半导体衬底; 在所述器件结构上形成的层间电介质层，其中在所述层间介质层中形成沟槽，所述沟槽包括并入的通孔沟槽和导电布线沟槽，并且所述导电布线沟槽位于所述通孔沟槽上; 以及填充在所述沟槽中的导电层，其中所述导电层与所述器件结构电连接; 其中所述导电层包括由所述导电材料包围的导电材料和纳米管/线层。其中，导电层包括由导电材料包围的导电材料和纳米管/线层。该结构的导电层具有较好的导热性，导电性和较高的抗电迁移能力，能有效防止金属离子向外扩散。

77. 发明申请

US20120168863A1 Semiconductor Structure and Method for Manufacturing the Same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120168863A1
公开(公告)日：2012-07-05
申请号：US13258642
申请日：2011-03-04
申请人： Huilong Zhu , Haizhou Yin , Zhijong Luo , Qingqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijong Luo , Qingqing Liang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78648 , H01L21/84 , H01L27/1203
摘要： Semiconductor structure and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device is formed on an SOI substrate comprising an SOI layer, a buried insulating layer, a buried semiconductor layer and a semiconductor substrate from top to bottom, and comprises: source/drain regions formed in the SOI layer; a gate formed on the SOI layer, wherein the source/drain regions are located at both sides of the gate; a back gate region formed by a portion of the buried semiconductor layer which is subjected to resistance reduction; and a first isolation structure and a second isolation structure which are located at both sides of the source/drain regions and extend into the SOI substrate; wherein the first isolation structure and the second isolation structure laterally adjoin the SOI layer at a first side surface and a second side surface respectively; the first isolation structure laterally adjoins the buried semiconductor layer at a third side surface; and the third side surface is located between the first side surface and the second side surface.
摘要翻译：公开了半导体结构及其制造方法。在一个实施例中，半导体器件形成在SOI衬底上，SOI衬底包括从顶部到底部的SOI层，掩埋绝缘层，埋入半导体层和半导体衬底，并且包括：在SOI层中形成的源/漏区; 形成在SOI层上的栅极，其中源极/漏极区域位于栅极的两侧; 由所述埋入半导体层的经受电阻降低的部分形成的背栅区; 以及位于源/漏区两侧并延伸到SOI衬底中的第一隔离结构和第二隔离结构; 其中所述第一隔离结构和所述第二隔离结构分别在第一侧表面和第二侧表面上横向邻接所述SOI层; 所述第一隔离结构在第三侧表面横向邻接所述掩埋半导体层; 第三侧面位于第一侧面和第二侧面之间。

78. 发明申请

US20120139048A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： MOSFET及其制造方法
公开(公告)号：US20120139048A1
公开(公告)日：2012-06-07
申请号：US13140744
申请日：2011-03-04
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/42384 , H01L29/4908 , H01L29/66772 , H01L29/78648
摘要： The present application discloses a MOSFET and a method for manufacturing the same. The MOSFET comprises an SOI chip comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; source/drain regions formed in the semiconductor layer; a channel region formed in the semiconductor layer and located between the source/drain regions; and a gate stack comprising a gate dielectric layer on the semiconductor layer, and a gate conductor on the gate dielectric layer, wherein the MOSFET further comprises a backgate formed in a portion of the semiconductor substrate below the channel region, and the backgate has a non-uniform doping profile, and wherein the buried insulating layer serves as a gate dielectric layer of the backgate. The MOSFET has an adjustable threshold voltage by changing the type of dopant and/or the doping profile in the backgate, and reduces a leakage current of the semiconductor device.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括SOI芯片，其包括半导体衬底，半导体衬底上的掩埋绝缘层和掩埋绝缘层上的半导体层; 在半导体层中形成的源/漏区; 形成在所述半导体层中且位于所述源/漏区之间的沟道区; 以及栅极堆叠，其包括在所述半导体层上的栅极电介质层和所述栅极介电层上的栅极导体，其中所述MOSFET还包括形成在所述沟道区域下方的所述半导体衬底的一部分中的后栅极， - 均匀的掺杂分布，并且其中所述掩埋绝缘层用作所述背栅的栅极电介质层。通过改变背栅中的掺杂剂类型和/或掺杂分布，MOSFET具有可调节的阈值电压，并且减小了半导体器件的漏电流。

79. 发明申请

US20120126244A1 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：浅层分离结构及其形成方法
公开(公告)号：US20120126244A1
公开(公告)日：2012-05-24
申请号：US13119004
申请日：2011-01-27
申请人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
IPC分类号： H01L29/12 , H01L29/16 , H01L21/761 , H01L27/04 , H01L21/762
CPC分类号： H01L29/7846 , H01L21/76224
摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减少了对于半导体器件性能的影响。

80. 发明申请

US20120097923A1 GRAPHENE DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：石墨装置及其制造方法
公开(公告)号：US20120097923A1
公开(公告)日：2012-04-26
申请号：US13140141
申请日：2011-02-24
申请人： Qingqing Liang , Zhi Jin , Wenwu Wang , Huicai Zhong , Xinyu Liu , Huilong Zhu
发明人： Qingqing Liang , Zhi Jin , Wenwu Wang , Huicai Zhong , Xinyu Liu , Huilong Zhu
IPC分类号： H01L29/786 , H01L29/165 , H01L21/336 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/778 , H01L29/1606 , H01L29/78603 , H01L29/78618 , H01L29/78684
摘要： The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.
摘要翻译：本发明提供了一种石墨烯器件结构及其制造方法，该器件结构包括石墨烯层; 与石墨烯层接触的栅极区域; 半导体掺杂区域形成在栅极区域的两个相对侧并与石墨烯层接触，其中半导体掺杂区域与栅极区域隔离; 在栅极区域上形成的触点和形成在半导体掺杂区域上的触点。通过半导体掺杂区域增加石墨烯器件的开关比，而不增加石墨烯材料的带隙，即不影响材料的迁移率或器件的速度，从而增加石墨烯材料的适用性在CMOS设备中。

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