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71. 发明授权

US5554551A Method of manufacture of an EEPROM cell with self-aligned thin dielectric area 失效
标题翻译：具有自对准薄介电区域的EEPROM单元的制造方法
公开(公告)号：US5554551A
公开(公告)日：1996-09-10
申请号：US344005
申请日：1994-11-23
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517 , Y10S438/981
摘要： An EEPROM cell is made by forming a first dielectric layer on a substrate, forming a tunnel mask with an tunnel opening used for etching the dielectric layer to form a tunnel window, doping a region of the substrate through the tunnel window and stripping the tunnel mask. A spacer frame is made about the perithery of the window over the first doped region of the substrate. A second dielectric layer is formed over the first doped region within the spacer frame which is then removed. Tunnel oxide is deposited on the exposed surface of the first doped region, a floating gate layer is deposited, mask and etched. The mask is stripped Ions are implanted into buried N+ source/drain regions through exposed surfaces of the gate oxide near the floating gate. A blanket interconductor layer covers the device. A control gate layer is deposited, mask and etched. The control gate mask is then removed.
摘要翻译：通过在衬底上形成第一电介质层，形成具有用于蚀刻电介质层的隧道开口的隧道掩模以形成隧道窗口，通过隧道窗口掺杂衬底的区域并剥离隧道掩模来制造EEPROM单元。围绕衬底的第一掺杂区域上的窗口的外面形成间隔框架。第二介电层形成在间隔框架内的第一掺杂区域上，然后将其去除。隧道氧化物沉积在第一掺杂区域的暴露表面上，沉积浮栅，掩模和蚀刻。掩模被剥离通过浮栅附近的栅极氧化物的暴露表面将离子注入掩埋的N +源极/漏极区。毯子互导层覆盖该设备。控制栅极层被沉积，掩模和蚀刻。然后移除控制门掩模。

72. 发明授权

US5512770A MOSFET device structure three spaced-apart deep boron implanted channel regions aligned with gate electrode of NMOSFET device 失效
标题翻译： MOSFET器件结构三个间隔开的深硼注入沟道区域与NMOSFET器件的栅电极对准
公开(公告)号：US5512770A
公开(公告)日：1996-04-30
申请号：US427213
申请日：1995-04-24
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/10 , H01L29/78 , H01L29/167 , H01L29/207 , H01L29/227 , H01L31/0288
CPC分类号： H01L29/66553 , H01L21/823412 , H01L29/1083 , H01L29/6659 , H01L29/7836 , H01L29/66537 , H01L29/66545
摘要： This invention describes a device structure and a method of forming the device structure using a polysilicon spacer formed on the edges of the gate electrode forming a gate structure with a cavity. The channel area is self aligned through this cavity. A fully overlapped Lightly-Doped-Drain structure is used to improve device characteristics for submicron devices. A deep boron implant region, self aligned through the gate structure, is used to improve punch through voltage.
摘要翻译：本发明描述了使用形成在具有空腔的栅极结构的栅电极的边缘上形成的多晶硅间隔来形成器件结构的器件结构和方法。通道区域通过该腔体自对准。完全重叠的轻掺杂结构用于提高亚微米器件的器件特性。通过栅极结构自对准的深硼注入区域用于提高穿通电压。

73. 发明授权

US5506167A Method of making a high resistance drain junction resistor in a SRAM 失效
标题翻译：在SRAM中制作高电阻漏极结电阻的方法
公开(公告)号：US5506167A
公开(公告)日：1996-04-09
申请号：US421000
申请日：1995-04-13
申请人： Hwi-Huang Chen , Gary Hong
发明人： Hwi-Huang Chen , Gary Hong
IPC分类号： H01L27/11 , H01L21/70
CPC分类号： H01L27/1112 , Y10S438/934
摘要： An improved SRAM resistor structure having implanted therein ions of an material in the surface layer of a drain junction region juxtaposed to an overlying metal contact layer providing the benefits of high resistance, low energy consumption, a single ion implantation step in an easily controlled process while producing a precise resistance desired and a method of making the SRAM resistor structure.
摘要翻译：一种改进的SRAM电阻器结构，其中注入了与上覆金属接触层并列的漏极结区域的表面层中的材料的离子，提供了高电阻，低能耗的优点，易于控制的过程中的单一离子注入步骤，产生所需的精确电阻和制造SRAM电阻器结构的方法。

74. 发明授权

US5496747A Split-gate process for non-volatile memory 失效
标题翻译：非易失性存储器的分流过程
公开(公告)号：US5496747A
公开(公告)日：1996-03-05
申请号：US100422
申请日：1993-08-02
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A split-gate memory cell and its fabrication are described. The semiconductor substrate is of a first conductivity type. The process begins by forming a conductive gate overlying the substrate, but electrically insulated therefrom by a layer of a first dielectric material. The gate comprises a first layer of conductive material, a second layer of dielectric material, and a third layer also composed of a second conductive layer. First and second sidewall dielectric spacers are formed adjacent to the first edge and the second opposing edge, respectively of the gate. Ions are implanted into the substrate. Those ions comprise a species of an opposite conductivity type. The ions are implanted at a substantial acute angle relative to a vertical angle with respect to the substrate. A third conductive material is deposited upon the second conductive layer and the first and second sidewall dielectric spacers. The third conductive material is in electrical contact with the second conductive layer.
摘要翻译：描述了分闸存储器单元及其制造。半导体衬底是第一导电类型。该过程开始于形成覆盖衬底的导电栅极，但是通过第一电介质材料层与其电绝缘。栅极包括导电材料的第一层，第二介电材料层，以及也由第二导电层构成的第三层。分别与栅极的第一边缘和第二相对边缘相邻地形成第一和第二侧壁电介质间隔物。离子植入衬底。这些离子包括相反导电类型的物质。离子相对于衬底相对于垂直角以大的锐角植入。第三导电材料沉积在第二导电层和第一和第二侧壁电介质间隔物上。第三导电材料与第二导电层电接触。

75. 发明授权

US5494839A Dual photo-resist process for fabricating high density DRAM 失效
标题翻译：用于制造高密度DRAM的双光刻工艺
公开(公告)号：US5494839A
公开(公告)日：1996-02-27
申请号：US237352
申请日：1994-05-03
申请人： Gary Hong , Chen-Chiu Hsue
发明人： Gary Hong , Chen-Chiu Hsue
IPC分类号： H01L21/027 , H01L21/3213 , H01L21/8242
CPC分类号： H01L27/10852 , H01L21/0274 , H01L21/32139 , Y10S438/943
摘要： A dual photo-resist process for fabricating capacitor plates of a DRAM is disclosed including the step of forming a capacitor on a semiconductor IC surface. A first plurality of photo-resist regions which are separated from each other by spaces are then formed on the capacitor plate layer. At least one second photo-resist region is then formed on the capacitor plate layer which partially fills a space between, and is adjacent to one of, two of the first photo-resist regions. The capacitor plate layer is then etched below the spaces between the first and second photo-resist regions to form a plurality of individual capacitor plates including one capacitor plate for each DRAM cell.
摘要翻译：公开了一种用于制造DRAM的电容器板的双光阻工艺，包括在半导体IC表面上形成电容器的步骤。然后在电容器板层上形成通过间隔彼此分开的第一多个光致抗蚀剂区域。然后在电容器板层上形成至少一个第二光刻抗蚀剂区域，其部分地填充两个第一光致抗蚀剂区域之间的空间，并且邻近其中之一。然后在第一和第二光致抗蚀剂区域之间的空间下方蚀刻电容器板层，以形成多个单独的电容器板，其包括用于每个DRAM单元的一个电容器板。

76. 发明授权

US5482879A Process of fabricating split gate flash memory cell 失效
标题翻译：制造分裂栅极闪存单元的过程
公开(公告)号：US5482879A
公开(公告)日：1996-01-09
申请号：US439917
申请日：1995-05-12
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A process of fabricating a split gate flash memory cell first forms a stacked-gate structure on a face of a substrate. The stacked-gate structure includes a tunnel oxide, a polysilicon floating gate, an inter-poly dielectric and a first polysilicon control gate. A drain region is formed into the substrate at one side of the stacked-gate structure, and is self-aligned with the stacked-gate structure. Thermal oxidation is performed to form sidewall oxides on the sidewalls of the stacked-gate structure, and gate oxide on the substrate. A second polysilicon control gate is deposited over the first polysilicon control gate, sidewall oxides and gate oxide, and is connected with the first polysilicon control gate to form a common control gate. A source region is formed in the substrate at another side of the stacked-gate structure, and is self-aligned with the substantially upright portion of the second polysilicon control gate located at the another side of the stacked-gate structure.
摘要翻译：首先制造分离栅闪存单元的工艺首先在基板的表面上形成堆叠栅极结构。堆叠栅极结构包括隧道氧化物，多晶硅浮动栅极，多晶硅电介质和第一多晶硅控制栅极。在层叠栅极结构的一侧形成漏极区，并与层叠栅结构自对准。进行热氧化以在堆叠栅极结构的侧壁上形成侧壁氧化物，并在基板上形成栅极氧化物。第二多晶硅控制栅极沉积在第一多晶硅控制栅极，侧壁氧化物和栅极氧化物上，并且与第一多晶硅控制栅极连接以形成公共控制栅极。源极区域形成在层叠栅极结构的另一侧的衬底中，并且与位于堆叠栅极结构的另一侧的第二多晶硅控制栅极的基本上直立的部分自对准。

77. 发明授权

US5464785A Method of making a flash EPROM device having a drain edge P+ implant 失效
标题翻译：制造具有漏极边缘P +植入物的闪速EPROM器件的方法
公开(公告)号：US5464785A
公开(公告)日：1995-11-07
申请号：US346866
申请日：1994-11-30
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/8247
CPC分类号： H01L27/11517
摘要： A MOSFET device has a floating gate and a control gate formed over a lightly P- doped semiconductor substrate with an N+ source region and an N+ drain region, includes a tunnel oxide dielectric layer on the substrate. A stack of gate layers includes a floating gate conductor overlying the first dielectric layer, an interconductor, ONO, dielectric layer over the floating gate conductor, and a control gate electrode over the interconductor dielectric layer. A P+, ion implanted, drain edge region is adjacent to the drain region in the substrate. The N+ source region and the N+ drain region are self-aligned with the stack, and an ion implanted N- region in the substrate is formed beneath the N+ source. Source/drain implant regions comprises arsenic ions implanted at between about 30 keV and about 100 keV and between about 1E15 cm.sup.-2 and about 8E15 cm.sup.-2. In manufacture a sacrificial layer is formed over the stack, then etched away from the device to form, with a mask, a deep trench adjacent to the source region and a trench adjacent the drain region between the edges of the stack and the mask.
摘要翻译： MOSFET器件具有浮置栅极和形成在具有N +源极区域和N +漏极区域的轻掺杂半导体衬底上的控制栅极，在衬底上包括隧道氧化物介电层。一叠栅极层包括覆盖在第一介电层上的浮动栅极导体，在浮动栅极导体上的互导体，ONO，介电层，以及在导体间介质层上的控制栅电极。 P +离子注入的漏极边缘区域与衬底中的漏极区域相邻。 N +源极区和N +漏极区与堆叠自对准，并且在N +源的下方形成衬底中的离子注入的N区。源极/漏极注入区域包括在约30keV至约100keV和约1E15cm-2至约8E15cm-2之间注入的砷离子。在制造中，在堆叠上形成牺牲层，然后从器件蚀刻掉与掩模相邻的深沟槽和邻近堆叠边缘和掩模之间的漏极区域的沟槽。

78. 发明授权

US5460991A Method of making high coupling ratio flash EEPROM device 失效
标题翻译：制造高耦合率闪存EEPROM器件的方法
公开(公告)号：US5460991A
公开(公告)日：1995-10-24
申请号：US405229
申请日：1995-03-16
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11521
摘要： A method of fabricating an erasable electrical programmable read only memory, (EEPROM), device has been developed. This device results in a high capacitive coupling ratio cell due to the ability of the described process to maintain the tunneling region at minimum dimensions. This in turn is accomplished by the novel sidewall image transfer, and removal processes described in this invention.
摘要翻译：已经开发了制造可擦除电可编程只读存储器（EEPROM）装置的方法。由于所描述的过程将隧道区域维持在最小尺寸的能力，该器件导致高电容耦合比单元。这又通过本发明中描述的新颖的侧壁图像转印和去除方法来实现。

79. 发明授权

US5460988A Process for high density flash EPROM cell 失效
标题翻译：高密度闪存EPROM单元的工艺
公开(公告)号：US5460988A
公开(公告)日：1995-10-24
申请号：US231811
申请日：1994-04-25
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L21/336 , H01L21/8247 , H01L21/265
CPC分类号： H01L29/66825 , H01L27/11556
摘要： A method and structure for manufacturing a high-density EPROM or flash memory cell is described. A structure having silicon islands is formed from a device-well that has been implanted with a first conductivity-imparting dopant, over a silicon substrate. A first dielectric layer surrounds the vertical surfaces of the silicon islands, whereby the first dielectric layer is a gate oxide. A first conductive layer is formed over vertical surfaces of the first dielectric layer, and acts as the floating surrounding-gate for the memory cell. A source region is formed in the device-well by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant, and surrounds the base of the silicon islands. A drain region is in the top of the silicon islands, formed by implanting with a second and opposite conductivity-imparting dopant to the first conductivity-imparting dopant. A thin dielectric layer surrounds the silicon islands, over the source region and under the first conductive layer, and acts as a tunnel oxide for the memory cell. A second dielectric layer is formed over vertical surfaces of the first conductive layer, and horizontally over the source region, and is an interpoly dielectric. A second conductive layer is formed over vertical surfaces of the second dielectric layer, and is the control gate for the memory cell.
摘要翻译：描述了用于制造高密度EPROM或闪存单元的方法和结构。具有硅岛的结构由在硅衬底上已被注入第一导电赋予掺杂剂的器件阱形成。第一电介质层围绕硅岛的垂直表面，由此第一介电层是栅极氧化物。在第一介电层的垂直表面上形成第一导电层，并且用作存储单元的浮动周围栅极。源极区通过向第一导电赋予掺杂剂注入第二和相反的导电赋予掺杂剂并围绕硅岛的基底而形成在器件中。漏极区位于硅岛的顶部，通过将第二和相反的赋予导电性的掺杂剂注入第一导电赋予掺杂剂而形成。薄介电层围绕硅岛，在源极区域和第一导电层下方，并且用作存储器单元的隧道氧化物。第二电介质层形成在第一导电层的垂直表面上，并且在源极区域上水平地形成，并且是多晶硅间电介质。在第二电介质层的垂直表面上形成第二导电层，并且是用于存储单元的控制栅极。

80. 发明授权

US5457061A Method of making top floating-gate flash EEPROM structure 失效
标题翻译：制造顶部浮栅闪存EEPROM结构的方法
公开(公告)号：US5457061A
公开(公告)日：1995-10-10
申请号：US275269
申请日：1994-07-15
申请人： Gary Hong , Chen-Chiu Hsue
发明人： Gary Hong , Chen-Chiu Hsue
IPC分类号： H01L21/336 , H01L21/8247 , H01L21/266
CPC分类号： H01L29/66825 , H01L27/11517
摘要： A method for forming, and a resultant structure of, a top floating gate FLASH EEPROM cell are described. There is a first insulating structure over a silicon substrate, whereby the first insulating structure is a gate oxide. A first conductive structure is formed over the first insulating structure, whereby the first conductive structure is a control gate. There is a first insulating layer over the surfaces of the first conductive structure, whereby the first insulating layer is an interpoly dielectric. There is a second conductive structure formed over the first insulating layer and over a portion of the silicon substrate adjacent to the first insulating structure, whereby the second conductive structure is a floating gate. A second insulating layer is formed between the silicon substrate and the second conductive structure, whereby the second insulating layer is a tunnel oxide. Active regions in the silicon substrate, implanted with a conductivity-imparting dopant, are formed under the second insulating layer but are horizontally a distance from the first insulating structure.
摘要翻译：描述了用于形成顶部浮置栅极FLASH EEPROM单元的方法和结果。在硅衬底上存在第一绝缘结构，由此第一绝缘结构是栅极氧化物。在第一绝缘结构上形成第一导电结构，由此第一导电结构是控制栅极。在第一导电结构的表面上存在第一绝缘层，由此第一绝缘层是互聚电介质。在第一绝缘层上形成第二导电结构，并且与第一绝缘结构相邻的硅衬底的一部分上方形成第二导电结构，由此第二导电结构是浮栅。在硅衬底和第二导电结构之间形成第二绝缘层，由此第二绝缘层是隧道氧化物。在第二绝缘层的下方形成硅衬底中注入导电性赋予剂的有源区，但与水平方向距离第一绝缘结构。

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