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71. 发明申请

US20090057908A1 WIRE BOND PADS 有权
标题翻译：电线棒
公开(公告)号：US20090057908A1
公开(公告)日：2009-03-05
申请号：US11849409
申请日：2007-09-04
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/49
CPC分类号： H01L24/03 , H01L2224/05001 , H01L2224/05073 , H01L2224/05553 , H01L2224/05624 , H01L2224/05647 , H01L2224/05681 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014
摘要： A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads.
摘要翻译：引线接合焊盘和制造引线接合焊盘的方法。该方法包括：提供衬底; 在所述基板的顶表面上形成导电层; 将导电层图案化成间隔开的多个引线接合焊盘; 以及在相邻引线接合焊盘之间的空间中在基板的顶表面上形成保护电介质层，在与键合焊盘的共面顶表面共面的空间中的电介质层的顶表面。

72. 发明申请

US20090032909A1 SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS 失效
标题翻译：带切割停止区域的半导体焊盘，用于减少芯片边缘/角落的裂纹传播
公开(公告)号：US20090032909A1
公开(公告)日：2009-02-05
申请号：US11833348
申请日：2007-08-03
申请人： Peter J. Brofman , Jon Alfred Casey , Ian D. Melville , David L. Questad , Wolfgang Sauter , Thomas Anthony Wassick
发明人： Peter J. Brofman , Jon Alfred Casey , Ian D. Melville , David L. Questad , Wolfgang Sauter , Thomas Anthony Wassick
IPC分类号： H01L23/58 , H01L21/64
CPC分类号： H01L21/563 , H01L23/3192 , H01L23/562 , H01L23/585 , H01L2224/73203 , H01L2924/01057
摘要： Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.
摘要翻译：结构及其形成方法。该结构包括半导体衬底，半导体衬底上的晶体管和半导体衬底顶部的N个互连层，N为正整数。晶体管电耦合到N个互连层。该结构还包括在N个互连层的顶部上的第一介电层和在第一介电层的顶部上的P个裂纹停止区，P是正整数。该结构还包括在第一电介质层的顶部上的第二电介质层。 P裂纹停止区域的每个裂纹停止区域被第一介电层和第二介电层完全包围。该结构还包括在第二电介质层的顶部上的底部填充层。第二电介质层夹在第一介电层和底部填充层之间。

73. 发明授权

US07459785B2 Electrical interconnection structure formation 失效
标题翻译：电互连结构形成
公开(公告)号：US07459785B2
公开(公告)日：2008-12-02
申请号：US11941165
申请日：2007-11-16
申请人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
发明人： Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Christopher David Muzzy , Wolfgang Sauter
IPC分类号： H01L23/52 , H01L23/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/03912 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05027 , H01L2224/05558 , H01L2224/05572 , H01L2224/05599 , H01L2224/10126 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/11912 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2224/05552
摘要： An electrical interconnection structure. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.
摘要翻译：电互连结构。该电气结构包括一个衬底，该衬底包括导电焊盘和该衬底上的第一介电层和该导电焊盘。第一介电层包括通孔。金属层形成在第一介电层之上和通孔内。第二电介质层形成在金属层上。在通孔内形成球限制金属化层。在球限制金属化层的表面上形成光致抗蚀剂层。在光致抗蚀剂层的第一开口内形成第一焊球，在光致抗蚀剂层的第二开口内形成第二焊球。

74. 发明申请

US20080191322A1 PREVENTION OF BACKSIDE CRACKS IN SEMICONDUCTOR CHIPS OR WAFERS USING BACKSIDE FILM OR BACKSIDE WET ETCH 有权
公开(公告)号：US20080191322A1
公开(公告)日：2008-08-14
申请号：US12107303
申请日：2008-04-22
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/58 , H01L21/31 , H01L21/302
CPC分类号： H01L29/34 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/10253 , H01L2924/15174 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.

75. 发明授权

US07329951B2 Solder bumps in flip-chip technologies 有权
标题翻译：倒装芯片技术的焊点
公开(公告)号：US07329951B2
公开(公告)日：2008-02-12
申请号：US10908083
申请日：2005-04-27
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/03 , H01L23/3171 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05023 , H01L2224/05073 , H01L2224/05124 , H01L2224/05558 , H01L2224/05562 , H01L2224/05567 , H01L2224/05568 , H01L2224/05572 , H01L2224/05583 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05671 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/1148 , H01L2224/11849 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要： A solder bump structure and method for forming the same. The structure includes (a) a dielectric layer including a dielectric layer top surface (b) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface; (c) a patterned support/interface layer on the dielectric layer top surface and thicker than the electrically conducting bond pad in the reference direction, wherein the patterned support/interface layer comprises a hole and a trench, wherein the hole is directly above the electrically conducting bond pad, and wherein the trench is not filled by any electrically conducting material; and (d) an electrically conducting solder bump filling the hole and electrically coupled to the electrically conducting bond pad.
摘要翻译：一种焊料凸块结构及其形成方法。该结构包括：（a）介电层，包括电介质层顶表面（b）与电介质层顶表面直接物理接触的导电接合焊盘; （c）在电介质层顶表面上的图案化支撑/界面层，并且比参考方向上的导电接合焊盘厚，其中所述图案化支撑/界面层包括孔和沟槽，其中所述孔直接位于电气导电接合焊盘，并且其中所述沟槽未被任何导电材料填充; 和（d）填充该孔并电耦合到导电接合焊盘的导电焊料凸块。

76. 发明授权

US07323780B2 Electrical interconnection structure formation 有权
标题翻译：电互连结构形成
公开(公告)号：US07323780B2
公开(公告)日：2008-01-29
申请号：US11164107
申请日：2005-11-10
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/52 , H01L23/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/03912 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05027 , H01L2224/05558 , H01L2224/05572 , H01L2224/05599 , H01L2224/10126 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/11912 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2224/05552
摘要： An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.
摘要翻译：电互连结构及其形成方法。该电气结构包括一个衬底，该衬底包括导电焊盘和该衬底上的第一介电层和该导电焊盘。第一介电层包括通孔。金属层形成在第一介电层之上和通孔内。第二电介质层形成在金属层上。在通孔内形成球限制金属化层。在球限制金属化层的表面上形成光致抗蚀剂层。在光致抗蚀剂层的第一开口内形成第一焊球，在光致抗蚀剂层的第二开口内形成第二焊球。

77. 发明申请

US20070200229A1 CHIP UNDERFILL IN FLIP-CHIP TECHNOLOGIES 有权
标题翻译：芯片技术中的芯片
公开(公告)号：US20070200229A1
公开(公告)日：2007-08-30
申请号：US11276380
申请日：2006-02-27
申请人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter , David Questad
发明人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter , David Questad
IPC分类号： H01L21/50 , H01L23/34
CPC分类号： H01L21/563 , H01L23/3128 , H01L24/10 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/29 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/13 , H01L2224/13099 , H01L2224/14 , H01L2224/1403 , H01L2224/14051 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81194 , H01L2224/8121 , H01L2224/81815 , H01L2224/83194 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/00 , H01L2924/3512
摘要： A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括（a）基板和（b）包括N个芯片焊球，N是正整数的芯片，并且N个芯片焊球与基板电接触。半导体结构还包括（c）分别在芯片的第一，第二，第三和第四角部处并夹在芯片和基板之间的第一，第二，第三和第四角底部填充区域。半导体结构还包括（d）夹在芯片和衬底之间的主要底部填充区域。第一，第二，第三和第四角底部填充区域，并且主底部填充区域基本上占据芯片和基板之间的整个空间。第一，第二，第三和第四角底部填充区域的角底层填充材料与主要底部填充区域的主要底部填充材料不同。

78. 发明申请

US20070176288A1 SOLDER WALL STRUCTURE IN FLIP-CHIP TECHNOLOGIES 失效
标题翻译：卷芯技术中的焊接墙结构
公开(公告)号：US20070176288A1
公开(公告)日：2007-08-02
申请号：US11275867
申请日：2006-02-01
申请人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
发明人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L23/562 , H01L24/11 , H01L2224/05001 , H01L2224/05008 , H01L2224/05024 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/056 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/00014 , H01L2924/00
摘要： A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.
摘要翻译：其形成结构及其方法。半导体结构包括与第一半导体芯片直接物理接触的第一半导体芯片和N个焊料凸块，其中N是正整数。半导体结构还包括在第一半导体芯片的周边上的第一焊料壁，使得第一焊料壁形成围绕N个焊料凸点的闭环。

79. 发明授权

US07112470B2 Chip dicing 失效
标题翻译：芯片切片
公开(公告)号：US07112470B2
公开(公告)日：2006-09-26
申请号：US10711383
申请日：2004-09-15
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L21/48
CPC分类号： H01L21/78
摘要： A semiconductor structure and method for chip dicing. The method comprises the steps of (a) providing a semiconductor substrate; (b) forming first and second device regions of first and second chips, respectively, in and at top of the semiconductor substrate, wherein the first and second chips are separated by a semiconductor border region of the semiconductor substrate; (c) forming N interconnect layers directly above the semiconductor border region and the first and second device regions, wherein N is a positive integer, wherein each layer of the N interconnect layers comprises an etchable portion directly above the semiconductor border region, and wherein the etchable portions of the N interconnect layers form a continuous etchable block; (d) removing the continuous etchable block by etching; and (e) cutting with a laser through the semiconductor border region via an empty space of the removed continuous etchable block to separate the first and second chips.
摘要翻译：一种用于芯片切割的半导体结构和方法。该方法包括以下步骤：（a）提供半导体衬底; （b）分别在半导体衬底中和顶部形成第一和第二芯片的第一和第二器件区域，其中第一和第二芯片由半导体衬底的半导体边界区域分开; （c）在半导体边界区域和第一和第二器件区域正上方形成N个互连层，其中N是正整数，其中N个互连层的每层包括直接在半导体边界区域上方的可蚀刻部分，并且其中 N互连层的可蚀刻部分形成连续的可蚀刻块; （d）通过蚀刻去除连续的可蚀刻块; 以及（e）通过所述被去除的连续可蚀刻块的空白空间，用激光切割所述半导体边界区域以分离所述第一和第二芯片。

80. 发明申请

US20060197228A1 SINGLE MASK PROCESS FOR VARIABLE THICKNESS DUAL DAMASCENE STRUCTURES, OTHER GREY-MASKING PROCESSES, AND STRUCTURES MADE USING GREY-MASKING 审中-公开
标题翻译：单一掩模过程，可变厚度双重DAMASCENE结构，其他灰色掩蔽过程和使用灰色掩蔽的结构
公开(公告)号：US20060197228A1
公开(公告)日：2006-09-07
申请号：US10906752
申请日：2005-03-04
申请人： Timothy Daubenspeck , Jeffrey Gambino , Kevin Ostrowski , Wolfgang Sauter
发明人： Timothy Daubenspeck , Jeffrey Gambino , Kevin Ostrowski , Wolfgang Sauter
IPC分类号： H01L23/48
CPC分类号： H01L21/31144 , G03F1/50 , H01L21/3083 , H01L21/32139 , H01L21/76807 , H01L21/76808 , H01L21/76816 , H01L21/76885 , H01L2221/1021
摘要： By using a multiple grey tone mask with at least two greys in semiconductor manufacture, multiple wiring thicknesses can now be made in a single level where previously only one wiring thickness could be provided. For example, power and signal wires of different thicknesses in a single layer can be provided.
摘要翻译：通过在半导体制造中使用具有至少两个灰度的多灰度蒙版掩模，现在可以在单一级别中进行多个布线厚度，其中先前只能提供一个布线厚度。例如，可以提供单层中不同厚度的功率和信号线。

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