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71. 发明授权

US08667256B1 Systems and method for managing divergent threads in a SIMD architecture 有权
标题翻译：用于管理SIMD架构中的发散线程的系统和方法
公开(公告)号：US08667256B1
公开(公告)日：2014-03-04
申请号：US12476088
申请日：2009-06-01
申请人： Brett W. Coon , John Erik Lindholm
发明人： Brett W. Coon , John Erik Lindholm
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/30181 , G06F9/322
摘要： One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is a branch instruction, determining that the program instruction is not a return or break instruction, determining whether the program instruction includes a set-synchronization bit, and updating an active program counter, where the manner in which the active program counter is updated depends on a branch instruction type.
摘要翻译：被配置为管理线程组中的发散线程的计算系统的一个实施例包括配置成存储至少一个令牌和多线程处理单元的堆栈。多线程处理单元被配置为执行获取程序指令，确定程序指令是分支指令，确定程序指令不是返回或中断指令的步骤，确定程序指令是否包括设置同步位并且更新活动程序计数器，其中活动程序计数器的更新方式取决于分支指令类型。

72. 发明授权

US08312254B2 Indirect function call instructions in a synchronous parallel thread processor 有权
标题翻译：同步并行线程处理器中的间接函数调用指令
公开(公告)号：US08312254B2
公开(公告)日：2012-11-13
申请号：US12054255
申请日：2008-03-24
申请人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills , John Erik Lindholm
发明人： Brett W. Coon , John R. Nickolls , Lars Nyland , Peter C. Mills , John Erik Lindholm
IPC分类号： G06F9/00
CPC分类号： G06F9/38 , G06F9/30054 , G06F9/30101 , G06F9/3851 , G06F9/3885
摘要： An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.
摘要翻译：间接分支指令将地址寄存器作为参数，以便为单指令多线程（SIMT）处理器架构提供间接函数调用能力。间接分支指令用于实现间接函数调用，虚函数调用和switch语句，以提高处理性能，与使用连续的测试和分支链相比。

73. 发明授权

US08237705B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08237705B2
公开(公告)日：2012-08-07
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

74. 发明授权

US08223158B1 Method and system for connecting multiple shaders 有权
标题翻译：连接多个着色器的方法和系统
公开(公告)号：US08223158B1
公开(公告)日：2012-07-17
申请号：US11613018
申请日：2006-12-19
申请人： John Erik Lindholm , Michael C. Shebanow , Jerome F. Duluk, Jr.
发明人： John Erik Lindholm , Michael C. Shebanow , Jerome F. Duluk, Jr.
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A method and system for connecting multiple shaders are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of configuring a set of shaders in a user-defined sequence within a modular pipeline (MPipe), allocating resources to execute the programming instructions of each of the set of shaders in the user-defined sequence to operate on the data unit, and directing the output of the MPipe to an external sink.
摘要翻译：公开了一种用于连接多个着色器的方法和系统。具体地，本发明的一个实施例提出了一种方法，其包括以下步骤：在模块化流水线（MPipe）内以用户定义的序列配置一组着色器，分配资源以执行所述一组用户定义的序列中的着色器在数据单元上操作，并将MPipe的输出引导到外部接收器。

75. 发明授权

US08200940B1 Reduction operations in a synchronous parallel thread processing system with disabled execution threads 有权
标题翻译：具有禁用执行线程的同步并行线程处理系统中的还原操作
公开(公告)号：US08200940B1
公开(公告)日：2012-06-12
申请号：US12164492
申请日：2008-06-30
申请人： John Erik Lindholm
发明人： John Erik Lindholm
IPC分类号： G06F15/00 , G06F15/76 , G06F17/00 , G06T1/00
CPC分类号： G06F9/5066 , G06F9/3001 , G06F9/30036 , G06F9/3851 , G06F9/3887
摘要： A system and method for successfully performing reduction operations in a multi-threaded SIMD (single-instruction multiple-data) system while one or more threads are disabled allows for the reduction operations to be performed without a performance penalty compared with performing the same operation with all of the threads enabled. The source data for each intermediate computation of the reduction operation is remapped by a configurable crossbar as needed to avoid using invalid data from the disabled threads. The remapping function is transparent to the user and enables correct execution of order invariant reduction operations and order dependent prefix-reduction operations.
摘要翻译：在一个或多个线程被禁用的情况下，在多线程SIMD（单指令多数据）系统中成功执行还原操作的系统和方法允许与执行相同操作相比执行还原操作而没有性能损失，所有线程启用。减少操作的每个中间计算的源数据根据需要由可配置的交叉开关重新映射，以避免使用来自禁用线程的无效数据。重映射功能对于用户是透明的，并且能够正确执行订单不变减少操作和依赖于依赖于订单的前缀缩减操作。

76. 发明申请

US20120026171A1 PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR 有权
标题翻译：图形处理器的并行阵列架构
公开(公告)号：US20120026171A1
公开(公告)日：2012-02-02
申请号：US13269462
申请日：2011-10-07
申请人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
发明人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
IPC分类号： G06T15/50
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译：用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

77. 发明授权

US07979683B1 Multiple simultaneous context architecture 有权
标题翻译：多个同时上下文体系结构
公开(公告)号：US07979683B1
公开(公告)日：2011-07-12
申请号：US11696928
申请日：2007-04-05
申请人： John M. Danskin , John Erik Lindholm
发明人： John M. Danskin , John Erik Lindholm
IPC分类号： G06F9/40
CPC分类号： G06F9/461 , G06T1/00
摘要： Graphics processing elements are capable of processing multiple contexts simultaneously, reducing the need to perform time consuming context switches compared with processing a single context at a time. Processing elements of a graphics processing pipeline may be configured to support all of the multiple contexts or only a portion of the multiple contexts. Each processing element may be allocated to process a particular context or a portion of the multiple contexts in order to simultaneously process more than one context. The allocation of processing elements to the multiple contexts may be determined dynamically in order to improve graphics processing throughput.
摘要翻译：与一次处理单个上下文相比，图形处理元件能够同时处理多个上下文，减少了执行耗时的上下文切换的需要。图形处理流水线的处理元件可以被配置为支持多个上下文中的所有或上述多个上下文的一部分。可以分配每个处理元件以处理特定上下文或多个上下文的一部分，以便同时处理多于一个上下文。可以动态地确定处理元件到多个上下文的分配，以便提高图形处理吞吐量。

78. 发明申请

US20110074802A1 Architecture and Instructions for Accessing Multi-Dimensional Formatted Surface Memory 有权
标题翻译：用于访问多维格式化表面存储器的体系结构和说明
公开(公告)号：US20110074802A1
公开(公告)日：2011-03-31
申请号：US12890171
申请日：2010-09-24
申请人： John R. Nickolls , Brian Fahs , Lars Nyland , John Erik Lindholm , Richard Craig Johnson
发明人： John R. Nickolls , Brian Fahs , Lars Nyland , John Erik Lindholm , Richard Craig Johnson
IPC分类号： G06F12/00
CPC分类号： G06T1/60
摘要： One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.
摘要翻译：本发明的一个实施例提出了一种用于访问多维格式化图形表面存储器的程序的技术。称为“表面”的多维存储器对象以用户指定的数据或像素格式存储并以图形优化的布局布置，由使用表面指令的程序访问。可以使用一组存储器访问指令，例如加载，存储，减少和原子，称为表面指令，以访问表面。通过可配置的夹紧进行坐标界限检查。缓存行为也可以由表面指令指定。支持存储，缩小和原子表面指令的数据格式转换和打包到指定的存储格式。负载和原子表面指令支持从指定的存储格式进行数据格式转换和解包。

79. 发明授权

US07859548B1 Offloading cube map calculations to a shader 有权
标题翻译：将多维数据集地图计算卸载到着色器
公开(公告)号：US07859548B1
公开(公告)日：2010-12-28
申请号：US11551176
申请日：2006-10-19
申请人： John Erik Lindholm
发明人： John Erik Lindholm
IPC分类号： G09G5/00
CPC分类号： G06T15/04
摘要： Systems and methods for performing cube mapping computations using a shader program may reduce the need for fixed function cube mapping computation units in graphics processors. Therefore, die area is used more efficiently since a general purpose processing unit may be configured using shader program instructions to perform the cube mapping computations and other computations. The general purpose processing unit is configured to perform floating point computations to identify the cube map face that will be read and process the cube map coordinates. A fixed function unit is also configured to identify the cube map face that will be read to avoid passing the cube map face information from the general purpose processing unit to the fixed function unit.
摘要翻译：使用着色器程序执行立方体映射计算的系统和方法可能减少对图形处理器中固定功能立方体映射计算单元的需求。因此，由于可以使用着色器程序指令来配置通用处理单元来执行多维数据集映射计算和其他计算，所以可以更有效地使用管芯区域。通用处理单元被配置为执行浮点计算以识别要被读取的立方体贴面，并且处理立方体贴图坐标。固定功能单元还被配置为识别将被读取的立方体贴图面部，以避免将立方体贴图面部信息从通用处理单元传递到固定功能单元。

80. 发明授权

US07836276B2 System and method for processing thread groups in a SIMD architecture 有权
标题翻译：在SIMD架构中处理线程组的系统和方法
公开(公告)号：US07836276B2
公开(公告)日：2010-11-16
申请号：US11292614
申请日：2005-12-02
申请人： Brett W. Coon , John Erik Lindholm
发明人： Brett W. Coon , John Erik Lindholm
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/3838 , G06F9/3851 , G06F9/3869 , G06F9/3887
摘要： A SIMD processor efficiently utilizes its hardware resources to achieve higher data processing throughput. The effective width of a SIMD processor is extended by clocking the instruction processing side of the SIMD processor at a fraction of the rate of the data processing side and by providing multiple execution pipelines, each with multiple data paths. As a result, higher data processing throughput is achieved while an instruction is fetched and issued once per clock. This configuration also allows a large group of threads to be clustered and executed together through the SIMD processor so that greater memory efficiency can be achieved for certain types of operations like texture memory accesses performed in connection with graphics processing.
摘要翻译： SIMD处理器有效利用其硬件资源来实现更高的数据处理吞吐量。 SIMD处理器的有效宽度通过以数据处理侧的速率的一小部分计时SIMD处理器的指令处理侧，并且通过提供多个执行流水线（每个具有多个数据路径）来扩展。因此，在每个时钟获取和发出一个指令的同时实现更高的数据处理吞吐量。该配置还允许通过SIMD处理器将大组线程聚类并一起执行，使得可以针对某些类型的操作（如结合图形处理执行的纹理存储器访问）实现更高的存储器效率。

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