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71. 发明授权

US07825000B2 Method for integration of magnetic random access memories with improved lithographic alignment to magnetic tunnel junctions 有权
标题翻译：磁性随机存取存储器与磁性隧道结的改进的光刻对准的集成方法
公开(公告)号：US07825000B2
公开(公告)日：2010-11-02
申请号：US11850427
申请日：2007-09-05
申请人： Sivananda K. Kanakasabapathy , Solomon Assefa
发明人： Sivananda K. Kanakasabapathy , Solomon Assefa
IPC分类号： H01L21/76 , H01L21/00
CPC分类号： H01L43/12 , H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.
摘要翻译：包括磁隧道结（MTJ）装置的磁存储器件包括基片和前端线（FEOL）电路。形成在VA ILD层的顶表面上方的通过级（VA）层间绝缘（ILD）层，底部导体层和形成在MTI器件上的MTJ器件。包括对准标记的对准区域延伸穿过底部导体层并向下延伸到VA ILD层的顶表面下方的装置与MJT装置并置。

72. 发明授权

US07803639B2 Method of forming vertical contacts in integrated circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US07803639B2
公开(公告)日：2010-09-28
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

73. 发明申请

US20090291388A1 Method for Forming a Self-Aligned Hard Mask for Contact to a Tunnel Junction 失效
标题翻译：形成用于接触隧道结的自对准硬掩模的方法
公开(公告)号：US20090291388A1
公开(公告)日：2009-11-26
申请号：US12126245
申请日：2008-05-23
申请人： Solomon Assefa , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Sivananda K. Kanakasabapathy
IPC分类号： G03F7/004 , G03F7/26
CPC分类号： H01L29/82 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack.
摘要翻译：提供了在与设备中形成的MTJ自对准的半导体器件中形成硬掩模的方法。该方法包括以下步骤：在MTJ的磁性堆叠的上表面上形成硬掩模材料层; 在所述硬掩模材料层的上表面的至少一部分上形成抗反射涂层（ARC）层，所述ARC层被选择为通过湿法蚀刻可去除; 在所述ARC层的上表面的至少一部分上形成光致抗蚀剂层; 去除所述光致抗蚀剂层和所述ARC层的至少一部分，从而暴露所述硬掩模材料层的至少一部分; 蚀刻硬掩模材料层以去除硬掩模材料层的暴露部分; 并且在相同的处理步骤中执行湿条以去除ARC层和光致抗蚀剂层的剩余部分而不干扰磁性堆叠。

74. 发明申请

US20080157156A1 METHOD AND STRUCTURE FOR IMPROVED ALIGNMENT IN MRAM INTEGRATION 有权
标题翻译：在MRAM集成中改进对准的方法和结构
公开(公告)号：US20080157156A1
公开(公告)日：2008-07-03
申请号：US12050293
申请日：2008-03-18
申请人： Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： H01L29/00
CPC分类号： H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.
摘要翻译：用于实现半导体器件结构的对准的方法包括在该结构的较低级别内形成第一组和第二组对准标记，第二组对准标记与第一组对准标记相邻。在较低层上形成不透明层，包括第一组和第二组对准标记。对应于所述第一组对准标记的位置的不透明层的一部分被打开，以使第一组光学可见，而第二组对准标记最初保持被不透明层覆盖。使用光学可见的第一组对准标记图案化不透明层，其中在第一组在不透明层的图案化期间第一组变得损坏的情况下，第二组对准标记保持可用于随后的对准操作。

75. 发明授权

US06875700B2 Ion-Ion plasma processing with bias modulation synchronized to time-modulated discharges 失效
标题翻译：离子离子等离子体处理，具有与时间调制放电同步的偏置调制
公开(公告)号：US06875700B2
公开(公告)日：2005-04-05
申请号：US09820244
申请日：2001-03-28
申请人： Sivananda K. Kanakasabapathy , Lawrence J. Overzet
发明人： Sivananda K. Kanakasabapathy , Lawrence J. Overzet
IPC分类号： H01J37/32 , H01L21/00 , H01L21/302
CPC分类号： H01L21/67069 , H01J37/321 , H01J37/32422 , H01J37/32706
摘要： A system for plasma processing using electron-free ion-ion plasmas, wherein the substrate bias waveform is synched to a pulsed RF drive. A delay is included between the end of an RF drive pulse and the start of a bias pulse, to allow the electron population to drop to approximately zero. By using a source gas mixture which has highly electronegative components, substrate bombardment with negative ions can be achieved.
摘要翻译：一种使用无电子离子离子等离子体的等离子体处理系统，其中衬底偏置波形与脉冲RF驱动器同步。在RF驱动脉冲的结束和偏置脉冲的开始之间包括延迟，以允许电子群落下降到大约零。通过使用具有高电负性组分的源气体混合物，可以实现具有负离子的底物轰击。

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