专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07709892B2 Semiconductor device having freestanding semiconductor layer 有权
标题翻译：具有独立半导体层的半导体器件
公开(公告)号：US07709892B2
公开(公告)日：2010-05-04
申请号：US11426698
申请日：2006-06-27
申请人： Brent A. Anderson , Edward J. Nowak , BethAnn Rainey
发明人： Brent A. Anderson , Edward J. Nowak , BethAnn Rainey
IPC分类号： H01L29/94 , H01L27/88
CPC分类号： H01L21/02595 , H01L21/02667 , H01L21/2022 , H01L29/66795 , H01L29/785
摘要： A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.
摘要翻译：在传统的SOI或体衬底硅器件上提供独立半导体层的方法包括在单晶基底结构上形成非晶或多晶心轴。然后在心轴和基底结构上形成共形多晶半导体层，其中多晶层接触基底结构。然后将多晶半导体层重结晶，使其具有与基础结构基本相似的结晶度。因此，以高度控制其厚度和高度的方式形成独立的半导体层并保持厚度的均匀性。

72. 发明申请

US20100047972A1 SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：具有现场屏蔽的半导体结构和形成结构的方法
公开(公告)号：US20100047972A1
公开(公告)日：2010-02-25
申请号：US12610563
申请日：2009-11-02
申请人： William F. Clark, JR. , Edward J. Nowak
发明人： William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L21/336 , H01L21/762
CPC分类号： H01L29/861 , H01L29/402 , H01L29/417 , H01L29/6609 , H01L29/772 , H01L29/78648
摘要： Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.
摘要翻译：公开了在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。场屏蔽被夹在晶片上的上隔离层和下隔离层之间。局部互连延伸穿过上隔离层并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET的二极管的源极/漏极区域或二极管的阴极或阳极）。进入设备的电流，例如，在线路充电的后端，被远离上隔离层的局部互连分流，并进入场屏蔽。因此，不允许在上部隔离层中积聚电荷，而是从场屏蔽件渗入下部隔离层并进入下面的基板。该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障。

73. 发明授权

US07667527B2 Circuit to compensate threshold voltage variation due to process variation 失效
标题翻译：用于补偿由于过程变化引起的阈值电压变化的电路
公开(公告)号：US07667527B2
公开(公告)日：2010-02-23
申请号：US11561480
申请日：2006-11-20
申请人： William F. Clark, Jr. , Edward J. Nowak
发明人： William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H03K3/01
CPC分类号： G05F3/205
摘要： Structure and process for compensating threshold voltage variation due to process variation. The structure includes a circuit segmented into sub-blocks having a predetermined size corresponding to a characteristic length associated with a process variation. A local circuit is located in each circuit sub-block, and a reference signal coupled to each local circuit. The local circuit generates a compensation signal in response to the reference signal to adjust an electrical parameter of the respective sub-block to a predetermined value.
摘要翻译：用于补偿由于过程变化引起的阈值电压变化的结构和过程。该结构包括分割成具有对应于与过程变化相关联的特征长度的预定尺寸的子块的电路。本地电路位于每个电路子块中，并且参考信号耦合到每个本地电路。本地电路响应于参考信号产生补偿信号，以将相应子块的电参数调整到预定值。

74. 发明申请

US20100039853A1 Design Structure, Structure and Method of Using Asymmetric Junction Engineered SRAM Pass Gates 失效
标题翻译：使用不对称结工程SRAM通道门的设计结构，结构和方法
公开(公告)号：US20100039853A1
公开(公告)日：2010-02-18
申请号：US12190040
申请日：2008-08-12
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： G11C11/00 , G06F17/50
CPC分类号： G11C11/412
摘要： A design structure, structure and method of using and/or manufacturing structures having asymmetric junction engineered SRAM pass gates is provided. The method includes applying a voltage through asymmetric pull-down nFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain; applying a voltage through asymmetric pull-up pFETs with high junction leakage from their body to their source and low junction leakage from the body to their drain; and applying a voltage through asymmetrical pass gates which provide low leakage SOI logic.
摘要翻译：提供了使用和/或制造具有非对称结工程SRAM通孔的结构的设计结构，结构和方法。该方法包括通过非对称下拉nFET施加电压，其具有从其主体到其源极的高结泄漏以及从主体到其漏极的低结漏; 通过非对称上拉pFET施加电压，其具有从其主体到其源极的高结泄漏以及从主体到其漏极的低结漏; 并通过提供低泄漏SOI逻辑的非对称通孔施加电压。

75. 发明申请

US20100038720A1 STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING DUAL METAL GATE VT ROLL-UP STRUCTURE 有权
标题翻译：结构，设计结构和制造双金属门VT卷取结构的方法
公开(公告)号：US20100038720A1
公开(公告)日：2010-02-18
申请号：US12192517
申请日：2008-08-15
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L27/092 , G06F17/50
CPC分类号： H01L29/4983 , H01L21/28097 , H01L21/28105 , H01L29/42376 , H01L29/66545 , H01L29/78
摘要： A structure, design structure and method of manufacturing is provided for a dual metal gate Vt roll-up structure, e.g., multi-work function metal gate. The multi-work function metal gate structure comprises a first type of metal with a first work function in a central region and a second type of metal with a second work function in at least one edge region adjacent the central region. The first work-function is different from the second work function.
摘要翻译：为双金属栅极Vt卷起结构（例如多功能金属栅极）提供了一种结构，设计结构和制造方法。多功能金属栅极结构包括在中心区域具有第一功函数的第一类金属和在邻近中心区域的至少一个边缘区域中具有第二功函数的第二类金属。第一个功能与第二个功能不同。

76. 发明授权

US07649243B2 Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof 有权
标题翻译：结合多个晶面的半导体结构及其制造方法
公开(公告)号：US07649243B2
公开(公告)日：2010-01-19
申请号：US11556833
申请日：2006-11-06
申请人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interposed therebetween. The first doped region and the second doped region are of different polarity. The semiconductor structure also includes a channel stop dielectric layer located upon a horizontal surface of the semiconductor mesa over the second doped region. The semiconductor structure also includes a first device located using a sidewall and a top surface of the first end as a channel region, and a second device located using the sidewall and not the top surface of the second end as a channel. A related method derives from the foregoing semiconductor structure. Also included is a semiconductor circuit that includes the semiconductor structure.
摘要翻译：半导体结构包括位于隔离衬底上的半导体台面。半导体台面包括第一端，该第一端包括通过插入其间的隔离区域与第二掺杂区域分离的第一掺杂区域。第一掺杂区域和第二掺杂区域具有不同的极性。半导体结构还包括位于第二掺杂区域上的半导体台面的水平表面上的沟道阻挡介电层。半导体结构还包括使用第一端的侧壁和顶表面作为沟道区的第一器件，以及使用侧壁而不是第二端的顶表面作为沟道定位的第二器件。相关方法源于上述半导体结构。还包括包括半导体结构的半导体电路。

77. 发明授权

US07645650B2 Double gated transistor and method of fabrication 有权
标题翻译：双门控晶体管和制造方法
公开(公告)号：US07645650B2
公开(公告)日：2010-01-12
申请号：US11774663
申请日：2007-07-09
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/84
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.
摘要翻译：一种形成晶体管的方法。提供半导体衬底。图案化半导体衬底以提供第一本体边缘。在第一身体边缘附近提供第一费米能级的第一门结构。图案化半导体衬底以提供第二本体边缘。半导体衬底的第一和第二主体边缘限定晶体管体。在第二身体边缘附近设置第二费米能级的第二门结构。在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

78. 发明申请

US20090298250A1 BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：双极晶体管和后置栅极结构和方法
公开(公告)号：US20090298250A1
公开(公告)日：2009-12-03
申请号：US12536636
申请日：2009-08-06
申请人： Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L21/331
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203 , H01L29/0804 , H01L29/7327 , H01L29/78648
摘要： A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.
摘要翻译：公开了一种结构，其包括在体层上包括绝缘体层的衬底和在衬底的第一区域中的双极晶体管，所述双极晶体管包括绝缘体层中的发射极区域的至少一部分。另一公开的结构包括在衬底的第一区域中的反相双极晶体管，其包括体层上的绝缘体层，反相双极晶体管包括发射极区域，以及位于衬底的第二区域中的后栅极晶体管，其中背面背栅式晶体管的栅极导体和发射极区域的至少一部分处于相同的材料层中。还公开了一种将双极晶体管和后栅极晶体管组合在一起的结构的方法。

79. 发明申请

US20090243029A1 METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS 有权
标题翻译：定制SOI电路历史效应的方法，结构与设计结构
公开(公告)号：US20090243029A1
公开(公告)日：2009-10-01
申请号：US12055622
申请日：2008-03-26
申请人： Brent A. Anderson , Edward J. Nowak
发明人： Brent A. Anderson , Edward J. Nowak
IPC分类号： H01L21/762 , H01L21/76 , G06F17/50
CPC分类号： G06F17/5045 , H01L21/76229 , H01L21/84 , H01L27/1203
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a structure which comprises a high-leakage dielectric formed in a divot on each side of a segmented FET comprised of active silicon islands and gate electrodes thereon, and a low-leakage dielectric on the surface of the active silicon islands, adjacent the high-leakage dielectric, wherein the low-leakage dielectric has a lower leakage than the high-leakage dielectric. Also provided is a structure and method of fabricating the structure.
摘要翻译：设计结构体现在用于设计，制造或测试设计的机器可读介质中。该设计结构包括一种结构，该结构包括形成在由活性硅岛和栅极电极组成的分段FET的每一侧上的凹陷处的高泄漏电介质和在活性硅岛的表面上的低泄漏电介质高泄漏电介质，其中低泄漏电介质具有比高泄漏电介质低的泄漏。还提供了一种制造该结构的结构和方法。

80. 发明申请

US20090236632A1 FET HAVING HIGH-K, VT MODIFYING CHANNEL AND GATE EXTENSION DEVOID OF HIGH-K AND/OR VT MODIFYING MATERIAL, AND DESIGN STRUCTURE 审中-公开
标题翻译：具有高K，VT改性通道的FET和高K和/或VT修饰材料的栅极延伸和设计结构
公开(公告)号：US20090236632A1
公开(公告)日：2009-09-24
申请号：US12051049
申请日：2008-03-19
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/4908 , H01L29/42384 , H01L29/78687
摘要： A field effect transistor (FET) including a high dielectric constant (high-k), threshold voltage (Vt) modifying channel and a gate extension devoid of the high-k and/or Vt modifying material, and a related design structure, are disclosed. In one embodiment, a FET may include a gate having a channel region thereunder including a gate insulator portion of a high dielectric constant (high-k) material and a threshold voltage (Vt) modifying portion (e.g., of SiGe); and a gate extension having a region thereunder devoid of at least one of the high-k material or the Vt modifying portion.
摘要翻译：公开了包括高介电常数（high-k），阈值电压（Vt）修正通道和没有高k和/或Vt修饰材料的栅极延伸的场效应晶体管（FET）以及相关的设计结构。在一个实施例中，FET可以包括其下具有沟道区的栅极，其中包括高介电常数（高k）材料的栅极绝缘体部分和阈值电压（Vt）修改部分（例如SiGe）; 以及具有其上没有高k材料或Vt修改部分中的至少一个的区域的栅极延伸部。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式