专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07961498B2 Leakage compensation circuit for Dynamic Random Access Memory (DRAM) cells 有权
标题翻译：用于动态随机存取存储器（DRAM）单元的泄漏补偿电路
公开(公告)号：US07961498B2
公开(公告)日：2011-06-14
申请号：US12236302
申请日：2008-09-23
申请人： DiaaEldin S. Khalil , Arijit Raychowdhury , Muhammad M. Khellah , Ali Keshavarzi
发明人： DiaaEldin S. Khalil , Arijit Raychowdhury , Muhammad M. Khellah , Ali Keshavarzi
IPC分类号： G11C11/24
CPC分类号： G11C8/14 , G11C11/404 , G11C11/4085 , G11C11/4094
摘要： A Dynamic Random Access Memory (DRAM) cell comprising a leakage compensation circuit. The leakage compensation circuit allows a compensation current from a source to flow to the memory cell storage node of the DRAM cell to compensate the leakage current from the memory cell storage node of the DRAM cell to improve retention time.
摘要翻译：一种包括泄漏补偿电路的动态随机存取存储器（DRAM）单元。泄漏补偿电路允许来自源的补偿电流流向DRAM单元的存储单元存储节点，以补偿来自DRAM单元的存储单元存储节点的泄漏电流，以改善保持时间。

72. 发明申请

US20080162869A1 Address hashing to help distribute accesses across portions of destructive read cache memory 审中-公开
标题翻译：地址散列可帮助分布访问破坏性读缓存内存的部分
公开(公告)号：US20080162869A1
公开(公告)日：2008-07-03
申请号：US11648297
申请日：2006-12-29
申请人： Nam Sung Kim , Muhammad M. Khellah , Vivek De
发明人： Nam Sung Kim , Muhammad M. Khellah , Vivek De
IPC分类号： G06F12/02
CPC分类号： G06F12/0893 , G06F12/0864 , G11C2207/2245
摘要： For one disclosed embodiment, an apparatus may comprise cache memory circuitry including multiple portions of destructive read memory cells and access control circuitry to access portions of destructive read memory cells. The apparatus may also comprise address hash logic to receive an address and to generate a hashed address based at least in part on at least a portion of the received address using a hashing technique to help distribute accesses by the access control circuitry across different portions of destructive read memory cells. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，装置可以包括高速缓存存储器电路，其包括破坏性读取存储器单元的多个部分和访问破坏性读取存储器单元的部分的访问控制电路。该装置还可以包括地址散列逻辑以接收地址并且至少部分地基于所接收的地址的至少一部分使用散列技术来生成散列地址，以帮助分配访问控制电路在不同部分的破坏性的访问读取存储单元。还公开了其他实施例。

73. 发明公开

US20240161817A1 THREE-TRANSISTOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY GAIN CELL IN COMPLEMENTARY FIELD EFFECT TRANSISTOR PROCESS 审中-公开
公开(公告)号：US20240161817A1
公开(公告)日：2024-05-16
申请号：US17985753
申请日：2022-11-11
申请人： Charles Augustine , Seenivasan Subramaniam , Patrick Morrow , Muhammad M. Khellah
发明人： Charles Augustine , Seenivasan Subramaniam , Patrick Morrow , Muhammad M. Khellah
IPC分类号： G11C11/412 , G11C11/419 , H01L27/11
CPC分类号： G11C11/412 , G11C11/419 , H01L27/1104
摘要： Embodiments herein relate to a three-transistor gain cell which is provided using a complementary field-effect transistor device to achieve scaling. The cell includes an n-type layer arranged above a p-type layer. In one implementation, two nMOS transistors are arranged above one pMOS transistor and a conductive path is provided to connect the gate of one of the nMOS transistors to a storage node in the p-type layer, where the storage node is coupled to a drain of the pMOS transistor. In another implementation, one nMOS transistor is arranged above two pMOS transistors and a conductive path is provided to connect the gate of one of the pMOS transistors to a storage node in the n-type layer, where the storage node is coupled to a source of the nMOS transistor.

74. 发明申请

US20170279348A1 BI-DIRECTIONAL MULTI-MODE CHARGE PUMP 有权
公开(公告)号：US20170279348A1
公开(公告)日：2017-09-28
申请号：US15081445
申请日：2016-03-25
申请人： Jaydeep Kulkarni , Yong Shim , Pascal A. Meinerzhagen , Muhammad M. Khellah
发明人： Jaydeep Kulkarni , Yong Shim , Pascal A. Meinerzhagen , Muhammad M. Khellah
IPC分类号： H02M3/07 , H03K5/19 , H03K3/03
CPC分类号： H02M3/07 , H03K3/0315 , H03K5/19
摘要： Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.

75. 发明授权

US09678878B2 Disabling cache portions during low voltage operations 有权
公开(公告)号：US09678878B2
公开(公告)日：2017-06-13
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08 , G06F12/126 , G06F12/0864 , G06F12/0804 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

76. 发明授权

US09111600B2 Memory cell with improved write margin 有权
标题翻译：具有改善写入容限的存储单元
公开(公告)号：US09111600B2
公开(公告)日：2015-08-18
申请号：US13997633
申请日：2012-03-30
申请人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
发明人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
IPC分类号： G11C7/00 , G11C5/14 , G11C11/413
CPC分类号： G11C11/419 , G11C5/14 , G11C5/147 , G11C5/148 , G11C11/4074 , G11C11/412 , G11C11/413 , G11C11/417
摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
摘要翻译：描述了一种用于改善存储器单元中的写入裕度的装置和系统。在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段的脉冲信号。在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

77. 发明申请

US20140108733A1 DISABLING CACHE PORTIONS DURING LOW VOLTAGE OPERATIONS 审中-公开
标题翻译：在低电压运行期间禁用高速缓存部分
公开(公告)号：US20140108733A1
公开(公告)日：2014-04-17
申请号：US13652480
申请日：2012-10-16
申请人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
发明人： Christopher Wilkerson , Muhammad M. Khellah , Vivek De , Ming Zhang , Jaume Abella , Javier Carretero Casado , Pedro Chaparro Monferrer , Xavier Vera , Antonio Gonzalez
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F1/3243 , G06F12/0804 , G06F2212/1028 , Y02D10/13 , Y02D10/152
摘要： Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
摘要翻译：描述了在低电压操作期间禁用一个或多个高速缓存部分的方法和装置。在一些实施例中，一个或多个额外的比特可以用于高速缓存的一部分，其指示高速缓存的部分是否能够在Vccmin等级或更低的值下运行。还描述和要求保护其他实施例。

78. 发明申请

US20110085389A1 METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF A MEMORY ARRAY 有权
标题翻译：降低存储器阵列最小工作电压的方法和系统
公开(公告)号：US20110085389A1
公开(公告)日：2011-04-14
申请号：US12576868
申请日：2009-10-09
申请人： Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury
发明人： Muhammad M. Khellah , Bibiche M. Geuskens , Arijit Raychowdhury
IPC分类号： G11C7/00 , G11C8/00 , G11C5/14
CPC分类号： G11C11/4085 , G11C5/145 , G11C11/4074 , G11C11/417
摘要： A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.
摘要翻译：一种在存储器阵列的读取和/或写入操作期间降低存储器阵列的最小工作电压的方法和系统。在本发明的一个实施例中，存储器阵列的读取和/或写入字线的电压在存储器阵列的读取和/或写入操作期间升高或增加。通过这样做，存储器阵列中的NMOS器件被加强，并且在存储器阵列的读取和/或写入操作期间NMOS和PMOS器件之间的争用被减小。这有助于在存储器阵列的读取和/或写入操作期间降低或减少存储器阵列所需的VCCmin。

79. 发明申请

US20180175832A1 POWER SWITCHING CIRCUITRY INCLUDING POWER-UP CONTROL 审中-公开
公开(公告)号：US20180175832A1
公开(公告)日：2018-06-21
申请号：US15382076
申请日：2016-12-16
申请人： Suphachai Chai Sutanthavibul , Iqbal Rajwani , Anupama A. Thaploo , Surya Sasi Tallapragada , Daivik H. Bhatt , Lei Jiang , Stephen Kim , Pascal A. Meinerzhagen , Muhammad M. Khellah
发明人： Suphachai Chai Sutanthavibul , Iqbal Rajwani , Anupama A. Thaploo , Surya Sasi Tallapragada , Daivik H. Bhatt , Lei Jiang , Stephen Kim , Pascal A. Meinerzhagen , Muhammad M. Khellah
IPC分类号： H03K3/012 , H02M1/08
CPC分类号： H02M1/08 , H02M1/088 , H02M3/158 , H02M2001/0032 , H02M2001/0048 , H03K17/08122 , H03K17/6871 , H03K19/0013 , H03K19/0016 , H03K2017/0806 , H03K2217/0036 , Y02B70/1491
摘要： Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

80. 发明申请

US20120151235A1 METHODS AND SYSTEMS FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING ENTRY AND EXIT LATENCY REDUCTION FOR LOW POWER STATES 有权
标题翻译：能源效率和能源节约的方法和系统，包括进入和退出低功耗状态的减排
公开(公告)号：US20120151235A1
公开(公告)日：2012-06-14
申请号：US13333753
申请日：2011-12-21
申请人： Jawad Nasrullah , Kelvin Kwan , Jaydeep P. Kulkarni , Muhammad M. Khellah
发明人： Jawad Nasrullah , Kelvin Kwan , Jaydeep P. Kulkarni , Muhammad M. Khellah
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.
摘要翻译：描述了用于低功率状态的进入和退出延迟降低的系统和方法。在一个实施例中，计算机实现的方法发起节能低功率状态（例如，深度睡眠状态）以减少设备的功耗。该方法设置电源电压，为双电源阵列提供足够的电力以保持状态。逻辑在此低功耗状态下掉电。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式