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    • 73. 发明授权
    • Methods of forming copper-based conductive structures on semiconductor devices
    • 在半导体器件上形成铜基导电结构的方法
    • US08791014B2
    • 2014-07-29
    • US13422439
    • 2012-03-16
    • Xunyuan ZhangHoon KimChanro Park
    • Xunyuan ZhangHoon KimChanro Park
    • H01L21/768
    • H01L21/76879H01L21/28556H01L21/28562H01L21/31144H01L21/32134H01L21/76805H01L21/76816
    • Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.
    • 本文公开了在诸如晶体管的半导体器件上形成铜基导电结构的各种方法。 在一个示例中,该方法包括通过图案化的金属硬掩模层执行第一蚀刻工艺以限定绝缘材料层中的开口,通过绝缘材料层中的开口执行第二蚀刻工艺,该开口暴露一部分 下面的含铜结构,进行湿蚀刻处理以去除图案化的金属硬掩模层,通过绝缘材料层中的开口进行选择性金属沉积工艺,以选择性地在含铜结构上形成金属区域,之后 形成金属区域,在金属区域上方的开口中形成含铜结构体。
    • 75. 发明授权
    • Integrated circuits having improved metal gate structures and methods for fabricating same
    • 具有改进的金属栅结构的集成电路及其制造方法
    • US08552505B1
    • 2013-10-08
    • US13445719
    • 2012-04-12
    • Hoon KimKisik Choi
    • Hoon KimKisik Choi
    • H01L21/70
    • H01L29/66545H01L21/823842H01L29/4966
    • Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a PFET trench in a PFET region and an NFET trench in an NFET region of an interlayer dielectric material on a semiconductor surface. The NFET trench is partially filled with an N-type work function metal layer to define an inner cavity. The PFET trench and the inner cavity in the NFET trench are partially filled with a P-type work function metal layer to define a central void in each trench. In the method, the central voids are filled with a metal fill to form metal gate structures. A single recessing process is then performed to recess portions of each metal gate structure within each trench to form a recess in each trench above the respective metal gate structure.
    • 提供了用于制造集成电路的集成电路和方法。 在一个实施例中,制造集成电路的方法包括在半导体表面上的层间绝缘材料的NFET区域中的PFET区域中形成PFET沟槽和NFET沟槽。 NFET沟槽部分地填充有N型功函数金属层以限定内腔。 NFET沟槽中的PFET沟槽和内腔部分地填充有P型功函数金属层,以在每个沟槽中限定中心空隙。 在该方法中,中心空隙填充有金属填充物以形成金属栅极结构。 然后执行单个凹陷处理以在每个沟槽内凹入每个金属栅极结构的部分,以在相应的金属栅极结构上方的每个沟槽中形成凹陷。
    • 78. 发明申请
    • UNIT PIXEL OF COLOR IMAGE SENSOR AND PHOTO DETECTOR THEREOF
    • 彩色图像传感器及其检测器的单元像素
    • US20130056806A1
    • 2013-03-07
    • US13224876
    • 2011-09-02
    • Hoon Kim
    • Hoon Kim
    • H01L31/113
    • H01L27/14645
    • A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film having one surface thereof being in contact with the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel formed between the source and the drain and configured to form flow of an electric current between the source and drain.
    • 公开了图像传感器和光电检测器的单位像素。 本发明的光电检测器可以包括:光吸收部,被配置为通过以浮动结构形成来吸收光; 氧化膜,其一个表面与光吸收部分接触; 源极与氧化膜的另一个表面的一侧接触并且与光吸收部分分离,其间具有氧化膜; 漏极,面对源极,以与氧化膜的另一表面的另一侧接触,并与其间的氧化膜与光吸收部分分离; 以及形成在源极和漏极之间并且被配置为在源极和漏极之间形成电流的沟道的沟道。