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71. 发明授权

US09859362B2 Processing a semiconductor wafer 有权
公开(公告)号：US09859362B2
公开(公告)日：2018-01-02
申请号：US15151667
申请日：2016-05-11
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Hans-Joachim Schulze
IPC分类号： H01L29/06 , H01L29/739 , H01L29/861 , H01L21/02 , H01L21/04 , H01L21/308 , H01L21/67 , H01L21/66 , H01L29/10 , H01L29/16 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0634 , H01L21/02529 , H01L21/046 , H01L21/0475 , H01L21/3065 , H01L21/3081 , H01L21/3083 , H01L21/3086 , H01L21/67063 , H01L22/14 , H01L22/20 , H01L22/34 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/739 , H01L29/7395 , H01L29/7802 , H01L29/7811 , H01L29/861
摘要： A semiconductor wafer processing system for processing a semiconductor wafer is presented. The semiconductor wafer processing system comprises: a trench production apparatus configured to produce trenches in the semiconductor wafer, the trenches being arranged next to each other along a first lateral direction (X); a trench filling apparatus configured to epitaxially fill the trenches with a doped semiconductor material; and a controller operatively coupled to at least one of the trench production apparatus and the trench filling apparatus, wherein the controller is configured to control at least one of the trench production apparatus and the trench filling apparatus in dependence of a parameter, the parameter being indicative of at least one of a variation of dopant concentrations of the doped semiconductor material along the first lateral direction (X) that is to be expected when carrying out the epitaxially filling and a deviation of an expected average of the dopant concentrations from a predetermined nominal value.

72. 发明申请

US20170243828A1 Semiconductor Device and Method for Producing a Semiconductor Device 有权
公开(公告)号：US20170243828A1
公开(公告)日：2017-08-24
申请号：US15427428
申请日：2017-02-08
申请人： Infineon Technologies AG
发明人： Jochen Hilsenbeck , Jens Peter Konrath , Stefan Krivec
IPC分类号： H01L23/532 , H01L21/285 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/2855 , H01L21/28568 , H01L21/28575 , H01L21/76841 , H01L21/76843 , H01L21/76852 , H01L23/532 , H01L23/564 , H01L24/03 , H01L24/05 , H01L24/48 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/8083 , H01L2224/0345 , H01L2224/0347 , H01L2224/03612 , H01L2224/03614 , H01L2224/0391 , H01L2224/03914 , H01L2224/04042 , H01L2224/05018 , H01L2224/05082 , H01L2224/05124 , H01L2224/05147 , H01L2224/05188 , H01L2224/05551 , H01L2224/05561 , H01L2224/05566 , H01L2224/05599 , H01L2224/05688 , H01L2224/45099 , H01L2224/85375 , H01L2224/85399 , H01L2924/00014 , H01L2924/12036 , H01L2924/13055 , H01L2924/13091 , H01L2924/00 , H01L2924/0496 , H01L2924/01042 , H01L2924/01029 , H01L2924/01014 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface metallization layer having a front face and a back face directed towards the active zone, the front surface metallization layer being provided on the front face of the semiconductor body and being electrically connected to the active zone, and a first barrier layer, including amorphous molybdenum nitride, located between the active zone and the metallization layer. Further, a method for producing such a device is provided.

73. 发明申请

US20170221987A1 Semiconductor Device and a Method for Forming a Semiconductor Device 审中-公开
公开(公告)号：US20170221987A1
公开(公告)日：2017-08-03
申请号：US15414872
申请日：2017-01-25
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Hans-Joachim Schulze
IPC分类号： H01L29/06 , H01L21/265 , H01L29/66 , H01L29/78
CPC分类号： H01L29/0619 , H01L21/265 , H01L21/31155 , H01L29/1608 , H01L29/4238 , H01L29/66348 , H01L29/66666 , H01L29/7397 , H01L29/7827
摘要： A method for forming a semiconductor device includes forming an oxide layer on a semiconductor substrate. A first portion of the oxide layer forms a gate oxide of a transistor structure. The method further includes replacing or modifying a second portion of the oxide layer to obtain a contamination barrier layer structure comprising phosphorus. The contamination barrier layer structure is located at a distance of less than 10 μm from the first portion of the oxide layer.

74. 发明申请

US20170170264A1 Semiconductor Devices and a Circuit for Controlling a Field Effect Transistor of a Semiconductor Device 审中-公开
公开(公告)号：US20170170264A1
公开(公告)日：2017-06-15
申请号：US15374012
申请日：2016-12-09
申请人： Infineon Technologies AG
发明人： Anton Mauder , Wolfgang Bergner , Jens Peter Konrath , Dethard Peters , Reinhold Schoerner
IPC分类号： H01L29/06 , H01L29/872 , H01L27/06 , H01L29/78 , H01L29/739 , H01L29/16 , H01L29/808
摘要： A semiconductor device includes a plurality of drift regions of a plurality of field effect transistor structures arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a Schottky diode structure or metal-insulation-semiconductor gated diode structure arranged at the semiconductor substrate.

75. 发明授权

US09633957B2 Semiconductor device, a power semiconductor device, and a method for processing a semiconductor device 有权
公开(公告)号：US09633957B2
公开(公告)日：2017-04-25
申请号：US14555736
申请日：2014-11-28
申请人： Infineon Technologies AG
发明人： Jochen Hilsenbeck , Jens Peter Konrath , Thomas Frank , Roland Rupp
IPC分类号： H01L23/532 , H01L23/00 , H01L23/31 , H01L23/58 , H01L29/43
CPC分类号： H01L24/05 , H01L23/3121 , H01L23/585 , H01L24/03 , H01L24/06 , H01L29/0615 , H01L29/0847 , H01L29/1608 , H01L29/417 , H01L29/4238 , H01L29/43 , H01L29/7392 , H01L29/7396 , H01L29/74 , H01L29/7802 , H01L29/8083 , H01L2224/02166 , H01L2224/0345 , H01L2224/03452 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05558 , H01L2224/05623 , H01L2224/05624 , H01L2224/06181 , H01L2224/45124 , H01L2924/01014 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/0105 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/1203 , H01L2924/12031 , H01L2924/12032 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/141 , H01L2924/1421 , H01L2924/143 , H01L2924/1431 , H01L2924/1434 , H01L2924/1435 , H01L2924/1436 , H01L2924/1461 , H01L2924/3512
摘要： According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.

76. 发明申请

US20170012102A1 Method for Reducing Bipolar Degradation in an SIC Semiconductor Device and Semiconductor Device 有权
标题翻译：降低SIC半导体器件和半导体器件双极性降解的方法
公开(公告)号：US20170012102A1
公开(公告)日：2017-01-12
申请号：US15205811
申请日：2016-07-08
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Roland Rupp , Hans-Joachim Schulze
IPC分类号： H01L29/32 , H01L29/36 , H01L21/265 , H01L29/16
CPC分类号： H01L29/32 , H01L21/046 , H01L21/26506 , H01L29/1608 , H01L29/36 , H01L29/6606 , H01L29/8611
摘要： Disclosed is a method for forming a semiconductor device and a semiconductor device. The method includes: in a SiC semiconductor body, forming crystal defects in a first semiconductor region by introducing non-doping particles into the semiconductor body; and forming a second semiconductor region such that there is a pn junction between the first semiconductor region and the second semiconductor region.

77. 发明申请

US20160336396A1 Processing a Semiconductor Wafer 有权
标题翻译：处理半导体晶圆
公开(公告)号：US20160336396A1
公开(公告)日：2016-11-17
申请号：US15151667
申请日：2016-05-11
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Hans-Joachim Schulze
IPC分类号： H01L29/06 , H01L21/02 , H01L29/10 , H01L21/66 , H01L21/308 , H01L21/67 , H01L29/16 , H01L21/04
CPC分类号： H01L29/0634 , H01L21/02529 , H01L21/046 , H01L21/0475 , H01L21/3065 , H01L21/3081 , H01L21/3083 , H01L21/3086 , H01L21/67063 , H01L22/14 , H01L22/20 , H01L22/34 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/739 , H01L29/7395 , H01L29/7802 , H01L29/7811 , H01L29/861
摘要： A semiconductor wafer processing system for processing a semiconductor wafer is presented. The semiconductor wafer processing system comprises: a trench production apparatus configured to produce trenches in the semiconductor wafer, the trenches being arranged next to each other along a first lateral direction (X); a trench filling apparatus configured to epitaxially fill the trenches with a doped semiconductor material; and a controller operatively coupled to at least one of the trench production apparatus and the trench filling apparatus, wherein the controller is configured to control at least one of the trench production apparatus and the trench filling apparatus in dependence of a parameter, the parameter being indicative of at least one of a variation of dopant concentrations of the doped semiconductor material along the first lateral direction (X) that is to be expected when carrying out the epitaxially filling and a deviation of an expected average of the dopant concentrations from a predetermined nominal value.
摘要翻译：提出了一种用于处理半导体晶片的半导体晶片处理系统。半导体晶片处理系统包括：沟槽制造装置，被配置为在半导体晶片中产生沟槽，所述沟槽沿着第一横向方向（X）彼此相邻布置; 沟槽填充装置，被配置为用掺杂的半导体材料外延地填充所述沟槽; 以及控制器，其可操作地耦合到所述沟槽制造装置和所述沟槽填充装置中的至少一个，其中所述控制器被配置为根据参数来控制所述沟槽制造装置和所述沟槽填充装置中的至少一个，所述参数是指示性的沿着沿着第一横向方向（X）的掺杂半导体材料的掺杂剂浓度的变化中的至少一种，其在进行外延填充时是预期的，并且掺杂剂浓度的预期平均值与预定标称值的偏差。

78. 发明授权

US09384983B2 Method of manufacturing a vertical semiconductor device 有权
标题翻译：制造垂直半导体器件的方法
公开(公告)号：US09384983B2
公开(公告)日：2016-07-05
申请号：US14729407
申请日：2015-06-03
申请人： Infineon Technologies AG
发明人： Ralf Siemieniec , Jens Peter Konrath
IPC分类号： H01L29/872 , H01L21/266 , H01L29/861 , H01L29/06 , H01L29/808 , H01L21/768 , H01L29/66 , H01L21/04 , H01L29/16
CPC分类号： H01L21/266 , H01L21/0465 , H01L21/76895 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/6606 , H01L29/66121 , H01L29/66128 , H01L29/66143 , H01L29/66893 , H01L29/66909 , H01L29/8083 , H01L29/861 , H01L29/8618 , H01L29/872
摘要： A method for producing a vertical semiconductor device includes providing a semiconductor substrate having a first surface and comprising an n-doped first semiconductor layer, forming a hard mask on the first surface, the hard mask comprising openings defining first zones in the n-doped first semiconductor layer, implanting acceptor ions of a first maximum energy through the hard mask into the first zones, replacing the hard mask by an inverted mask comprising openings that are substantially complementary to the openings of the hard mask; implanting acceptor ions of a second maximum energy different to the first maximum energy through the inverted mask into second zones of the n-doped first semiconductor layer, and carrying out at least one temperature step to activate the acceptor ions in the first zones and the second zones.
摘要翻译：一种用于制造垂直半导体器件的方法包括提供具有第一表面并包括n掺杂的第一半导体层的半导体衬底，在第一表面上形成硬掩模，所述硬掩模包括在n掺杂的第一表面中限定第一区的开口通过硬掩模将第一最大能量的受主离子注入到第一区域中，通过包括与硬掩模的开口基本上互补的开口的倒置掩模代替硬掩模; 将与第一最大能量不同的第二最大能量的受体离子通过反相掩模注入到n掺杂的第一半导体层的第二区域中，并且执行至少一个温度步骤以激活第一区域中的受主离子，区域。

79. 发明申请

US20150263178A1 JFET AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译： JFET及其制造方法
公开(公告)号：US20150263178A1
公开(公告)日：2015-09-17
申请号：US14207733
申请日：2014-03-13
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Hans-Joachim Schulze , Ralf Siemieniec , Cedric Ouvrard
IPC分类号： H01L29/808 , H01L21/311 , H01L21/266 , H01L29/66
CPC分类号： H01L29/8083 , H01L21/266 , H01L29/1066 , H01L29/1608 , H01L29/36 , H01L29/407 , H01L29/66909
摘要： A JFET has a semiconductor body with a first surface and second surface substantially parallel to the first surface. A source metallization and gate metallization are arranged on the first surface. A drain metallization is arranged on the second surface. In a sectional plane substantially perpendicular to the first surface, the semiconductor body includes: a first semiconductor region in ohmic contact with the source and drain metallizations, at least two second semiconductor regions in ohmic contact with the gate metallization, spaced apart from one another, and forming respective first pn-junctions with the first semiconductor region, and at least one body region forming a second pn-junction with the first semiconductor region. The at least one body region is in ohmic contact with the source metallization. At least a portion of the at least one body region is, in a projection onto the first surface, arranged between the two second semiconductor regions.
摘要翻译： JFET具有半导体本体，其具有基本上平行于第一表面的第一表面和第二表面。源金属化和栅极金属化被布置在第一表面上。漏极金属化被布置在第二表面上。在基本上垂直于第一表面的截面中，半导体本体包括：与源极和漏极金属化欧姆接触的第一半导体区域，与栅极金属化欧姆接触的至少两个第二半导体区域彼此间隔开，以及与所述第一半导体区域形成相应的第一pn结，以及形成与所述第一半导体区域的第二pn结的至少一个体区。至少一个体区与源金属化欧姆接触。所述至少一个体区的至少一部分在所述第一表面上的突起中布置在所述两个第二半导体区之间。

80. 发明申请

US20150137143A1 Junction Field Effect Transistor Cell with Lateral Channel Region 有权
标题翻译：具有侧向通道区域的结场效应晶体管电池
公开(公告)号：US20150137143A1
公开(公告)日：2015-05-21
申请号：US14083023
申请日：2013-11-18
申请人： Infineon Technologies AG
发明人： Jens Peter Konrath , Hans-Joachim Schulze
IPC分类号： H01L29/808 , H01L29/10 , H01L29/423 , H01L21/265 , H01L21/266 , H01L29/16 , H01L29/66
CPC分类号： H01L29/8083 , H01L21/0465 , H01L21/26546 , H01L21/266 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/2003 , H01L29/66909
摘要： A junction field effect transistor cell of a semiconductor device includes a top gate region, a lateral channel region and a buried gate region arranged along a vertical direction. The lateral channel region includes first zones of a first conductivity type and second zones of a second conductivity type which alternate along a lateral direction perpendicular to the vertical direction. A pinch-off voltage of the junction field effect transistor cell does not depend, or only to a low degree depends, on a vertical extension of the lateral channel region.
摘要翻译：半导体器件的结型场效应晶体管单元包括沿着垂直方向布置的顶栅区域，横向沟道区域和掩埋栅极区域。横向通道区域包括第一导电类型的第一区域和沿垂直于垂直方向的横向方向交替的第二导电类型的第二区域。结型场效应晶体管单元的夹断电压不依赖于或仅在很小程度上取决于横向沟道区域的垂直延伸。

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