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71. 发明申请

US20100146610A1 NODE AUTHENTICATION AND NODE OPERATION METHODS WITHIN SERVICE AND ACCESS NETWORKS IN NGN ENVIRONMENT 有权
标题翻译： NGN环境中的服务和访问网络中的节点认证和节点操作方法
公开(公告)号：US20100146610A1
公开(公告)日：2010-06-10
申请号：US12667886
申请日：2008-07-04
申请人： Kwihoon Kim , Hyun-Woo Lee , Seng-Kyoun Jo , Jae-Young Ahn , Won Ryu , Byung-Sun Lee , Kyung-Pyo Jun
发明人： Kwihoon Kim , Hyun-Woo Lee , Seng-Kyoun Jo , Jae-Young Ahn , Won Ryu , Byung-Sun Lee , Kyung-Pyo Jun
IPC分类号： H04L9/32
CPC分类号： H04L63/08 , H04W12/06
摘要： Provided are node authentication and node operation methods within service and access networks for bundle authentication between the service and access networks in a next generation network (NGN). A method of authentication processing of a node (S-CSC-FE/I-CSC-FE (Serving Call Session Control Functional Entity/Interrogating Call Session Control Functional Entity)) within a service network for bundle authentication between service and access networks, the method including: receiving first authentication information about access authentication of a terminal from a first node within the service networks; requesting to receive second authentication information from a second node within the service network based on the first authentication information; and comparing the first authentication information with the second authentication information to authenticate the terminal.
摘要翻译：提供服务和接入网络中的节点认证和节点操作方法，用于在下一代网络（NGN）中的业务和接入网之间的捆绑认证。在服务网络内的用于服务和接入网络之间的捆绑认证的节点（S-CSC-FE / I-CSC-FE（服务呼叫会话控制功能实体/询问呼叫会话控制功能实体））的认证处理方法，方法，包括：从服务网络内的第一节点接收关于终端的接入认证的第一认证信息; 基于所述第一认证信息，请求从所述服务网络内的第二节点接收第二认证信息; 以及将所述第一认证信息与所述第二认证信息进行比较以认证所述终端。

72. 发明授权

US07619454B2 Clock generator for semiconductor memory apparatus 有权
标题翻译：半导体存储装置的时钟发生器
公开(公告)号：US07619454B2
公开(公告)日：2009-11-17
申请号：US12185855
申请日：2008-08-05
申请人： Hyun-Woo Lee
发明人： Hyun-Woo Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , G11C7/22 , G11C7/222 , H03K2005/00241
摘要： The clock generator for semiconductor memory apparatus which includes: a first divider configured to divide a frequency of a first internal clock generated by using an external clock; a first delay unit configured to delay an output of the first divider by first delay time; a second divider configured to divide a frequency of an output of the first delay unit; a second delay unit configured to delay the output of the second divider by second delay time; a phase comparator configured to compare a phase of the output of the first divider with a phase of the output of the second delay unit and output a result of the comparison; and a delay time setting unit configured to set the first delay time on the basis of the output of the phase comparator.
摘要翻译：一种用于半导体存储装置的时钟发生器，包括：第一分配器，被配置为分频通过使用外部时钟产生的第一内部时钟的频率; 第一延迟单元，被配置为将所述第一分频器的输出延迟第一延迟时间; 第二分频器，被配置为对所述第一延迟单元的输出的频率进行分频; 第二延迟单元，被配置为将所述第二分频器的输出延迟第二延迟时间; 相位比较器，被配置为将第一分频器的输出的相位与第二延迟单元的输出的相位进行比较，并输出比较结果; 以及延迟时间设定单元，被配置为基于相位比较器的输出来设定第一延迟时间。

73. 发明授权

US07567102B2 Delay locked loop circuit in semiconductor device and its control method 有权
标题翻译：半导体器件中的延迟锁定环路及其控制方法
公开(公告)号：US07567102B2
公开(公告)日：2009-07-28
申请号：US11987935
申请日：2007-12-06
申请人： Hyun-Woo Lee
发明人： Hyun-Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/095
摘要： A delay locked loop (DLL) device includes a first and a second input buffers for receiving an external clock, a multiplexer for selectively outputting a first and a second internal clocks based on a most significant bit (MSB) signal, a delay means for delaying the first and the second internal clock which is selected by the multiplexer, a phase detector for comparing a phase of the first internal clock with that of a feedback clock which is feedbacked from the delay means to thereby output a comparing signal, a low pass filter (LPF) mode generator for outputting a locking signal, which checks a locking state of the feedback clock based on the comparing signal and a first and a second control signals, to the delay means, and a low pass filter for receiving the comparing signal to inform whether or not the comparing signal is erroneous to the delay means.
摘要翻译：延迟锁定环（DLL）装置包括用于接收外部时钟的第一和第二输入缓冲器，用于基于最高有效位（MSB）信号选择性地输出第一和第二内部时钟的多路复用器，用于延迟的延迟装置由多路复用器选择的第一和第二内部时钟，相位检测器，用于将第一内部时钟的相位与从延迟装置反馈的反馈时钟的相位进行比较，从而输出比较信号;低通滤波器（LPF）模式发生器，用于输出锁定信号，该锁定信号基于比较信号和第一和第二控制信号检测反馈时钟的锁定状态到延迟装置;以及低通滤波器，用于接收比较信号通知比较信号是否对延迟装置是错误的。

74. 发明授权

US07385428B2 Digital delay locked loop capable of correcting duty cycle and its method 有权
标题翻译：数字延迟锁定环能够校正占空比及其方法
公开(公告)号：US07385428B2
公开(公告)日：2008-06-10
申请号：US11646054
申请日：2006-12-27
申请人： Hyun-Woo Lee , Jong-Tae Kwak
发明人： Hyun-Woo Lee , Jong-Tae Kwak
IPC分类号： H03L7/06
CPC分类号： H03K5/1565
摘要： An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.
摘要翻译：一种用于调整时钟信号的装置，包括：时钟复用单元，用于接收外部时钟信号，外部时钟条信号和反馈时钟信号，以便选择外部时钟信号和外部时钟条信号之一作为基于将所述外部时钟信号的相位与所述反馈时钟信号的相位进行比较的结果，所述时钟复用单元的输出信号; 以及用于响应于时钟多路复用单元的输出信号产生占空比校正时钟信号和反馈时钟信号的延迟锁定环（DLL）。

75. 发明申请

US20080111995A1 System and method for CD determination using an alignment sensor of a lithographic apparatus 有权
标题翻译：使用光刻设备的对准传感器进行CD确定的系统和方法
公开(公告)号：US20080111995A1
公开(公告)日：2008-05-15
申请号：US11599619
申请日：2006-11-15
申请人： Hyun-Woo Lee , Sami Musa
发明人： Hyun-Woo Lee , Sami Musa
IPC分类号： G01B11/02
CPC分类号： G03F7/70641 , G03F7/70625 , G03F9/7065 , G03F9/7076
摘要： A system and method for determining parameters such as critical dimension of a patterned structure and best focus condition of a lithographic apparatus, based on measurment of the intensity of a non-zero order of light diffracted from an experimental structure. The experimental structure includes a first array of lines and partially filled spaces having a period longer than the wavelength of the diffracted light. The experimental structure also includes a second array of lines and spaces, where the second array of lines and spaces comprise the partially filled spaces.
摘要翻译：基于从实验结构衍射的光的非零级的强度的测量，确定诸如图案化结构的临界尺寸和光刻设备的最佳聚焦条件的参数的系统和方法。实验结构包括具有比衍射光的波长长的周期的第一阵列阵列和部分填充空间。实验结构还包括线和空间的第二阵列，其中第二阵列的线和空间构成部分填充的空间。

76. 发明授权

US07372836B2 Method of transmitting control data in CDMA mobile communication system 有权
标题翻译： CDMA移动通信系统中发送控制数据的方法
公开(公告)号：US07372836B2
公开(公告)日：2008-05-13
申请号：US10115349
申请日：2002-04-03
申请人： Sung-Oh Hwang , Jae-Yoel Kim , Kook-Heui Lee , Sung-Ho Choi , Yong-Jun Kwak , Sung-Hoon Kim , Jin-Weon Chang , Ju-Ho Lee , Hyun-Woo Lee
发明人： Sung-Oh Hwang , Jae-Yoel Kim , Kook-Heui Lee , Sung-Ho Choi , Yong-Jun Kwak , Sung-Hoon Kim , Jin-Weon Chang , Ju-Ho Lee , Hyun-Woo Lee
IPC分类号： H04B7/216
CPC分类号： H04J13/0003 , H04B2201/70701 , H04L1/1671 , H04L1/1812 , H04W48/08 , H04W52/08 , H04W52/286
摘要： A device and method for configuring an UL-DPCCH. One or more UL-DPCCHs, especially a UL-DPCCH for supporting HSDPA, are constructed in code division multiplexing and transmitted according to the characteristics of control information. The UL-DPCCH of the present invention that delivers various kinds of control information can be configured flexibly and operate in compatibility with a conventional asynchronous mobile communication system.
摘要翻译：一种用于配置UL-DPCCH的设备和方法。根据控制信息的特性，一个或多个UL-DPCCH，特别是用于支持HSDPA的UL-DPCCH被构建在码分复用中并被发送。可以灵活地配置提供各种控制信息的本发明的UL-DPCCH，并与常规的异步移动通信系统兼容。

77. 发明授权

US07233577B2 Method for measuring confusion rate of a common packet channel in a CDMA communication system 有权
标题翻译： CDMA通信系统中公共分组信道的混淆速率测量方法
公开(公告)号：US07233577B2
公开(公告)日：2007-06-19
申请号：US09832237
申请日：2001-04-10
申请人： Sung-Ho Choi , Seong-Ill Park , Ho-Kyu Choi , Hyun-Woo Lee , Ki-Ho Jung
发明人： Sung-Ho Choi , Seong-Ill Park , Ho-Kyu Choi , Hyun-Woo Lee , Ki-Ho Jung
IPC分类号： H04Q7/00
CPC分类号： H04W52/325 , H04W24/10 , H04W28/18 , H04W48/12 , H04W52/12 , H04W52/143 , H04W52/146 , H04W52/322 , H04W52/50 , H04W52/58 , H04W74/002 , H04W74/008 , H04W74/0833
摘要： A method is disclosed for determining by a UTRAN a persistence value having a value between 0 and 1 for adjusting a number of access preambles from a plurality of UEs requiring assignment of a common packet channel (CPCH). The method includes the steps of counting a number of the access preambles detected in an access preamble period having a predetermined period; and determining the persistence value based on the number of counted access preambles. The persistence value is determined in a unit of transport format (TF), physical common packet channel (PCPCH), or CPCH set.
摘要翻译：公开了一种用于由UTRAN确定具有0和1之间的值的持续值以便调整来自需要分配公共分组信道（CPCH）的多个UE的接入前导码的数量的方法。该方法包括以下步骤：对具有预定周期的接入前导码周期中检测到的接入前导码数进行计数; 以及基于所计数的访问前导码的数量来确定所述持久性值。以传输格式（TF），物理公用分组信道（PCPCH）或CPCH集合为单位确定持久性值。

78. 发明申请

US20070103212A1 Digital delay locked loop capable of correcting duty cycle and its method 有权
标题翻译：数字延迟锁定环能够校正占空比及其方法
公开(公告)号：US20070103212A1
公开(公告)日：2007-05-10
申请号：US11646054
申请日：2006-12-27
申请人： Hyun-Woo Lee , Jong-Tae Kwak
发明人： Hyun-Woo Lee , Jong-Tae Kwak
IPC分类号： H03L7/06
CPC分类号： H03K5/1565
摘要： An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.
摘要翻译：一种用于调整时钟信号的装置，包括：时钟复用单元，用于接收外部时钟信号，外部时钟条信号和反馈时钟信号，以便选择外部时钟信号和外部时钟条信号之一作为基于将所述外部时钟信号的相位与所述反馈时钟信号的相位进行比较的结果，所述时钟复用单元的输出信号; 以及用于响应于时钟多路复用单元的输出信号产生占空比校正时钟信号和反馈时钟信号的延迟锁定环（DLL）。

79. 发明授权

US07212578B2 Transmit diversity apparatus and method using two or more antennas 有权
标题翻译：使用两个或多个天线的发射分集装置和方法
公开(公告)号：US07212578B2
公开(公告)日：2007-05-01
申请号：US09935553
申请日：2001-08-22
申请人： Hyun-Woo Lee , Ho Kyu Choi , Yong-Jun Kwak , Sung-Jin Kim
发明人： Hyun-Woo Lee , Ho Kyu Choi , Yong-Jun Kwak , Sung-Jin Kim
IPC分类号： H04B7/02
CPC分类号： H04B7/0669 , H04B7/0678
摘要： A transmit diversity system having at least four antennas. A first adder adds a first spread signal obtained by spreading a first symbol pattern with a first orthogonal code to a second spread signal obtained by spreading the first symbol pattern with a second orthogonal code, and transmits the added signal through a first antenna. A second adder adds the first spread signal to a third spread signal obtained by spreading an inverted symbol pattern of the first symbol pattern with the second orthogonal code, and transmits the added signal through a second antenna. A third adder adds a fourth spread signal obtained by spreading a second symbol pattern with the first orthogonal code to a fifth spread signal obtained by spreading the second symbol pattern with the second orthogonal code, and transmits the added signal through a third antenna. A fourth adder adds the fourth spread signal to a sixth spread signal obtained by spreading an inverted symbol of the second symbol pattern with the second orthogonal code, and transmits the added signal through a fourth antenna.
摘要翻译：一种具有至少四个天线的发射分集系统。第一加法器将通过用第一正交码扩展第一符号模式而获得的第一扩展信号加到通过用第二正交码扩展第一符号模式而获得的第二扩展信号，并通过第一天线发送相加信号。第二加法器将第一扩展信号与通过用第二正交码扩展第一符号图案的反相符号图案而获得的第三扩展信号相加，并通过第二天线发送相加的信号。第三加法器将通过用第一正交码扩展第二符号模式而获得的第四扩展信号加到通过用第二正交码扩展第二符号模式而获得的第五扩展信号，并通过第三天线发送相加的信号。第四加法器将第四扩展信号与通过用第二正交码扩展第二符号模式的反相符号获得的第六扩展信号相加，并通过第四天线发送相加信号。

80. 发明授权

US07120132B2 Apparatus and method for synchronization of uplink synchronous transmission scheme in a CDMA communication system 有权
标题翻译： CDMA通信系统中上行同步传输方案的同步装置及方法
公开(公告)号：US07120132B2
公开(公告)日：2006-10-10
申请号：US09888914
申请日：2001-06-25
申请人： Sung-Ho Choi , Yong-Jun Kwak , Kook-Heui Lee , Hyun-Woo Lee , Seong-Ill Park , Ho-Kyu Choi
发明人： Sung-Ho Choi , Yong-Jun Kwak , Kook-Heui Lee , Hyun-Woo Lee , Seong-Ill Park , Ho-Kyu Choi
IPC分类号： H04B7/216 , H04J3/06
CPC分类号： H04W56/0005 , H04B1/707 , H04B1/7075
摘要： Disclosed is a method for synchronizing a scrambling code in a CDMA communication system including a UTRAN (UMTS Terrestrial Radio Access Network) and a plurality of user equipments (UEs), using orthogonal codes for identifying the UEs and a single scrambling code for identifying the UTRAN by the UEs, and employing an uplink synchronous transmission scheme (USTS) where the UEs synchronize frames of uplink dedicated physical channels (DPCHs) using the single scrambling code. The UEs receive a reference signal including reference time information provided from the UTRAN and transmit a random access channel (RACH) based on the reference time. The UTRAN receives the random access channels from the UEs to measure a propagation delay time (PD) of each random access channel signal from the UEs, and transmits a transmission time adjustment value calculated using the measured propagation delay time and a time offset τDPCH,n between a transmission time point of the reference signal and a transmission time point of a downlink DPCH. Each UE determines a transmission time of the uplink DPCH by receiving the transmission time adjustment value, and scrambles a message with the orthogonal code and a scrambling code generated at the reference time, at the transmission time so determined as to transmit the message over the uplink DPCH.
摘要翻译：公开了一种使用包括UTRAN（UMTS陆地无线电接入网）和多个用户设备（UE）的CDMA通信系统中的扰码进行同步的方法，使用用于识别UE的正交码和用于识别UTRAN的单个扰码并且使用上行链路同步传输方案（USTS），其中UE使用单个扰码来同步上行链路专用物理信道（DPCH）的帧。 UE接收包括从UTRAN提供的参考时间信息的参考信号，并且基于参考时间发送随机接入信道（RACH）。 UTRAN从UE接收随机接入信道以测量来自UE的每个随机接入信道信号的传播延迟时间（PD），并且发送使用测量的传播延迟时间和时间偏移τ DPCH，n参考信号的传输时间点与下行链路DPCH的传输时间点之间。每个UE通过接收传输时间调整值来确定上行链路DPCH的传输时间，并且在传输时刻在正确码和在参考时间产生的扰码进行加扰，从而确定为通过上行链路发送消息 DPCH。

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