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    • 73. 发明授权
    • Forward error correction apparatus and method in a high-speed data transmission system
    • 高速数据传输系统中的前向纠错装置和方法
    • US07137060B2
    • 2006-11-14
    • US10458204
    • 2003-06-11
    • Nam-Yul YuMin-Goo Kim
    • Nam-Yul YuMin-Goo Kim
    • H03M13/03H03M13/00
    • H03M13/658H03M13/1111H03M13/1117H03M13/112
    • A forward error correction method for decoding coded bits generated by low density parity check matrixes. The method comprises converting each of the coded bits into a log likelihood ratio (LLR) value, and applying the converted values to variable nodes; delivering messages applied to the variable nodes to check nodes; checking a message having a minimum value among the messages, and determining a sign of the message having the minimum value; receiving messages updated in the check nodes, adding up signs of the received messages and a sign of an initial message, applying a weighting factor of 1 when all signs are identical, and when all signs are not identical, updating a message of a variable node by applying a weighting factor; determining LLR of an initial input value; and hard-deciding values of the variable nodes, performing parity check on the hard decision values, and stopping the decoding when no error occurs.
    • 一种用于解码由低密度奇偶校验矩阵产生的编码比特的前向纠错方法。 该方法包括将每个编码比特转换成对数似然比(LLR)值,并将转换的值应用于可变节点; 传递应用于变量节点的消息以检查节点; 检查消息中具有最小值的消息,并确定具有最小值的消息的符号; 接收在校验节点中更新的消息,将接收到的消息的符号和初始消息的符号相加,当所有符号相同时应用加权因子1,并且当所有符号不相同时,更新变量节点的消息 通过应用加权因子; 确定初始输入值的LLR; 可变节点的硬判定值,硬判决值进行奇偶校验,无错误发生时停止解码。
    • 74. 发明申请
    • Antenna selection diversity apparatus and method in a broadband wireless communication system
    • 宽带无线通信系统中的天线选择分集装置及方法
    • US20060223476A1
    • 2006-10-05
    • US11392899
    • 2006-03-30
    • Seong-Wook SongYoung-Mo GuYong-Chul SongMin-Goo Kim
    • Seong-Wook SongYoung-Mo GuYong-Chul SongMin-Goo Kim
    • H04B1/06H04B7/00
    • H04B7/0811
    • An apparatus and method for improving antenna diversity in a receiver of a broadband wireless communication system using multiple antennas are provided. The receiver with the diversity apparatus uses a structure of multiple analog front ends, a structure for measuring antenna-by-antenna reception power values/Carrier-to-Interference plus Noise Ratios (CINRs) after Fast Fourier Transform (FFT) using a single analog front end, and a structure based on a single analog front end for measuring antenna-by-antenna reception power values after Analog-to-Digital (A/D) conversion without use of FFT. When a receive antenna is selected, the measured reception power values/CINRs are used. In a system for transmitting pilot signals with preamble data in a regular pattern, the receiver can have improved performance through a suitable frequency modulation process and can be implemented at low cost, as compared with that of the conventional antenna selection diversity.
    • 提供一种用于改善使用多个天线的宽带无线通信系统的接收机中的天线分集的装置和方法。 具有分集装置的接收机使用多个模拟前端的结构,用于使用单个模拟器在快速傅里叶变换(FFT)之后测量天线天线接收功率值/载波与干扰加噪声比(CINR)的结构 前端,以及基于单个模拟前端的结构,用于在不使用FFT的情况下测量模数(A / D)转换之后的天线接收功率值。 当选择接收天线时,使用测量的接收功率值/ CINR。 在用于以规则模式发送具有前导码数据的导频信号的系统中,与常规天线选择分集相比,接收机可以通过适当的频率调制过程具有改进的性能,并且可以以低成本实现。
    • 76. 发明申请
    • Apparatus and method for decoding low density parity check codes
    • 解码低密度奇偶校验码的装置和方法
    • US20050262420A1
    • 2005-11-24
    • US11133287
    • 2005-05-20
    • Sung-Jin ParkMin-Goo KimNam YuHan-Ju Kim
    • Sung-Jin ParkMin-Goo KimNam YuHan-Ju Kim
    • H04L27/18H03M13/00H03M13/11
    • H03M13/6566H03M13/1137
    • An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.
    • 提供了一种用于解码低密度奇偶校验(LDPC)码的装置和方法。 由多个单元存储器构成的存储器模块存储可靠性值。 可变节点处理器执行与变量节点相关联的计算,并且分别在列方向上更新存储器模块的数据。 检查节点处理器执行与校验节点相关联的计算,并分别更新存储器模块在行方向上的数据。 奇偶校验器确定所有错误是否已经被校正,使得执行迭代解码过程。 存储器访问控制模块选择要由可变节点处理器或校验节点处理器更新的单元存储器。