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71. 发明申请

US20130032777A1 Semiconductor Device and Manufacturing Method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130032777A1
公开(公告)日：2013-02-07
申请号：US13376237
申请日：2011-08-05
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/20 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/45 , B82Y10/00 , H01L29/1606 , H01L29/42316 , H01L29/66431 , H01L29/7781 , H01L29/78618 , H01L29/78684 , H01L51/0048 , H01L51/0562
摘要： The present invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the steps of providing a substrate on which a graphene layer or carbon nanotube layer is formed; exposing part of the graphene layer or carbon nanotube layer after forming a gate structure on the graphene layer or carbon nanotube layer, wherein the gate structure comprises a gate stack, a spacer and a cap layer, the cap layer is located on the gate stack, and the spacer surrounds the gate stack and the cap layer; epitaxially growing a semiconductor layer on the exposed graphene layer or carbon nanotube layer; and forming a metal contact layer on the semiconductor layer. In the present invention, the semiconductor layer is formed on the graphene layer or carbon nanotube layer, and then the metal contact layer is formed on the semiconductor layer, instead of forming the metal contact layer directly from the graphene layer or carbon nanotube layer. This facilitates to form the self-aligned source and drain contact plugs.
摘要翻译：本发明公开了一种半导体器件及其制造方法。该方法包括提供其上形成有石墨烯层或碳纳米管层的基板的步骤; 在石墨烯层或碳纳米管层上形成栅极结构之后暴露部分石墨烯层或碳纳米管层，其中栅极结构包括栅极堆叠，间隔物和覆盖层，盖层位于栅极叠层上，并且所述间隔件围绕所述栅极堆叠和所述盖层; 在暴露的石墨烯层或碳纳米管层上外延生长半导体层; 以及在所述半导体层上形成金属接触层。在本发明中，在石墨烯层或碳纳米管层上形成半导体层，然后在半导体层上形成金属接触层，而不是直接从石墨烯层或碳纳米管层形成金属接触层。这有助于形成自对准的源极和漏极接触插头。

72. 发明申请

US20130015497A1 SOURCE/DRAIN REGION, CONTACT HOLE AND METHOD FOR FORMING THE SAME 有权
标题翻译：源/排水区，接触孔及其形成方法
公开(公告)号：US20130015497A1
公开(公告)日：2013-01-17
申请号：US13119074
申请日：2011-02-18
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/768 , H01L23/48
CPC分类号： H01L29/0847 , H01L21/76805 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/78
摘要： An S/D region including a first region and a second region is provided. The first region is located, with at least a partial thickness, in the substrate. The second region is formed on the first region and made of a material different from that of the first region. A method for forming an S/D region is further provided, and the method includes: forming trenches at both sides of a gate stack structure in a substrate; forming a first semiconductor layer, wherein at least a part of the first semiconductor layer is filled into the trenches; and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer is made of a material different from that of the first semiconductor layer. A contact hole and a forming method thereof are also provided which may increase the contact area between a contact hole and a contact region, and reduce the contact resistance.
摘要翻译：提供包括第一区域和第二区域的S / D区域。第一区域在衬底中具有至少部分厚度。第二区域形成在第一区域上并且由与第一区域不同的材料制成。还提供了形成S / D区域的方法，该方法包括：在基板中的栅叠层结构的两侧形成沟槽; 形成第一半导体层，其中所述第一半导体层的至少一部分被填充到所述沟槽中; 以及在所述第一半导体层上形成第二半导体层，其中所述第二半导体层由与所述第一半导体层不同的材料制成。还提供接触孔及其形成方法，其可以增加接触孔和接触区域之间的接触面积，并降低接触电阻。

73. 发明申请

US20130001691A1 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130001691A1
公开(公告)日：2013-01-03
申请号：US13381075
申请日：2011-08-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/41733 , H01L21/76816 , H01L21/76882 , H01L21/76897 , H01L23/485 , H01L29/458 , H01L29/66636 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, and forming a gate structure on the SOI substrate; etching an SOI layer and a BOX layer of the SOI substrates on both sides of the gate structure, so as to form trenches exposing the BOX layer and extending partially into the BOX layer; forming metal sidewall spacers on sidewalls of the trenches, wherein the metal sidewall spacers is in contact with the SOI layer under the gate structure; forming an insulating layer filling partially the trenches, and forming a dielectric layer to cover the gate structure and the insulating layer; etching the dielectric layer to form first contact through holes that expose at least partially the insulating layer, and etching the insulating layer from the first contact through holes to form second contact through holes that expose at least partially the metal sidewall spacer; filling the first contact through holes and the second contact through holes to form contact vias, which are in contact with the metal sidewall spacers. The method provided by the present invention is capable of improving performance of semiconductor devices and alleviating manufacturing difficulty at the mean time.
摘要翻译：本发明提供一种制造半导体结构的方法，其包括：提供SOI衬底，并在SOI衬底上形成栅极结构; 在栅极结构的两侧蚀刻SOI衬底的SOI层和BOX层，以形成露出BOX层并部分延伸到BOX层的沟槽; 在所述沟槽的侧壁上形成金属侧壁间隔物，其中所述金属侧壁间隔物与所述栅极结构下的所述SOI层接触; 形成部分填充沟槽的绝缘层，形成覆盖栅结构和绝缘层的电介质层; 蚀刻所述介电层以形成至少部分地暴露所述绝缘层的第一接触通孔，以及从所述第一接触通孔蚀刻所述绝缘层以形成至少部分地暴露所述金属侧壁间隔物的第二接触通孔; 通过孔和第二接触通孔填充第一接触件以形成与金属侧壁间隔件接触的接触通孔。本发明提供的方法能够提高半导体装置的性能，同时能够减轻制造难度。

74. 发明申请

US20120292766A2 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：其半导体结构及其制造方法
公开(公告)号：US20120292766A2
公开(公告)日：2012-11-22
申请号：US12990990
申请日：2010-09-19
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/522 , H01L21/32051 , H01L21/76823 , H01L21/76838 , H01L21/76873 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises: providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.
摘要翻译：本发明提供一种半导体结构及其制造方法。该方法包括：提供包括半导体器件的半导体衬底; 在所述半导体衬底上沉积铜扩散阻挡层; 在铜扩散阻挡层上形成铜复合层; 根据铜互连的形状，将要形成铜互连的相应位置处的铜复合物分解成铜; 并且在下面蚀刻未分解的铜复合物和铜扩散阻挡层，以使半导体器件互连。本发明适用于制造集成电路中的互连。

75. 发明申请

US20120264262A1 Method for forming semiconductor structure 有权
标题翻译：半导体结构形成方法
公开(公告)号：US20120264262A1
公开(公告)日：2012-10-18
申请号：US13381014
申请日：2011-04-18
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823828 , H01L29/7833 , H01L29/7847 , H01L29/7848
摘要： The invention relates to a method for forming a semiconductor structure, comprising: providing a semiconductor substrate which comprises a dummy gate formed thereon, a spacer surrounding the dummy gate, source and drain regions formed on two sides of the dummy gate, respectively, and a channel region formed in the semiconductor substrate and below the dummy gate; removing the dummy gate to form a gate opening; forming a stressed material layer in the gate opening; performing an annealing to the semiconductor substrate, the stressed material layer having tensile stress characteristics during the annealing; removing the stressed material layer in the gate opening; and forming a gate in the gate opening. By the above steps, the stress memorization technique can be applied to the pMOSFET.
摘要翻译：本发明涉及一种形成半导体结构的方法，包括：提供包括形成在其上的虚拟栅极的半导体衬底，围绕伪栅极的间隔物，分别形成在虚拟栅极两侧的源区和漏区，以及形成在半导体衬底中并在虚拟栅极之下的沟道区; 去除虚拟门以形成门开口; 在闸门开口处形成应力材料层; 对所述半导体基板进行退火，所述应力材料层在退火时具有拉伸应力特性; 去除闸门开口中的应力材料层; 并在门开口形成门。通过上述步骤，可以将应力记忆技术应用于pMOSFET。

76. 发明申请

US20120235244A1 Semiconductor Structure and Method for Manufacturing the Same 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120235244A1
公开(公告)日：2012-09-20
申请号：US13380482
申请日：2011-04-18
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L27/088 , H01L29/772 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26586 , H01L21/28518 , H01L21/823814 , H01L21/823864 , H01L29/41775 , H01L29/456 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/7835
摘要： A method for manufacturing a semiconductor structure comprises: providing a substrate, forming an active region on the substrate, forming a gate stack or a dummy gate stack on the active region, forming a source extension region and a drain extension region at opposite sides of the gate stack or dummy gate stack, forming a spacer on sidewalls of the gate stack or dummy gate stack, and forming a source and a drain on portions of the active region exposed by the spacer and the gate stack or dummy gate stack; removing at least a part of a source-side portion of the spacer, such that the source-side portion of the spacer has a thickness less than that of a drain-side portion of the spacer; and forming a contact layer on portions of the active region exposed by the spacer and the gate stack or dummy gate stack. Correspondingly, the present invention further provides a semiconductor structure. The present invention is beneficial to the reduction of the contact resistance of the source extension region and meanwhile can also reduce the parasitic capacitance between the gate and the drain extension region.
摘要翻译：一种用于制造半导体结构的方法，包括：提供衬底，在衬底上形成有源区，在有源区上形成栅叠层或虚栅极叠层，在源极延伸区和漏极延伸区的相对两侧形成栅极堆叠或伪栅极堆叠，在栅极堆叠或伪栅极堆叠的侧壁上形成间隔物，以及在由间隔物和栅极堆叠或伪栅极堆叠暴露的有源区域的部分上形成源极和漏极; 去除所述间隔物的源极侧部分的至少一部分，使得所述间隔物的源极侧部分的厚度小于所述间隔物的漏极侧部分的厚度; 以及在由间隔件和栅极堆叠或虚拟栅极堆叠暴露的有源区域的部分上形成接触层。相应地，本发明还提供一种半导体结构。本发明有益于降低源延伸区域的接触电阻，同时还可以减小栅极和漏极延伸区域之间的寄生电容。

77. 发明申请

US20120217553A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：US20120217553A1
公开(公告)日：2012-08-30
申请号：US13063737
申请日：2010-06-28
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L21/823443 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate formed on the substrate, and a source and drain formed in the substrate and disposed at two sides of the gate; raised portions formed on the source and the drain, respectively, a height of the raised portions being approximate to a height of the gate; and a metal silicide layer and contact holes formed on the raised portions and on the gate. By virtue of the raised portions added to the source/drain in an embodiment of the present invention, the height difference between the gate and the source/drain may be decreased, such that the formation of the contact holes becomes much easier.
摘要翻译：本发明提供一种半导体结构，包括：基板; 形成在基板上的栅极，以及形成在基板中并设置在栅极两侧的源极和漏极; 分别形成在源极和漏极上的凸起部分，凸起部分的高度接近门的高度; 以及形成在凸起部分和栅极上的金属硅化物层和接触孔。由于在本发明的一个实施例中，由于在源极/漏极上添加的凸起部分，栅极和源极/漏极之间的高度差可能会降低，使得接触孔的形成变得容易得多。

78. 发明申请

US20120181664A1 SUBSTRATE STRUCTURE FOR SEMICONDUCTOR DEVICE FABRICATION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：用于半导体器件制造的衬底结构及其制造方法
公开(公告)号：US20120181664A1
公开(公告)日：2012-07-19
申请号：US13264063
申请日：2010-04-14
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/06 , H01L21/308 , H01L29/24 , H01L29/16
CPC分类号： H01L31/0392 , H01L31/035281 , Y02E10/50
摘要： The present invention proposes a strip plate structure and a method of manufacturing the same. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing, each of said strip plates including a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets, each strip sheet alternately abutting either the first surfaces or the second surfaces of two adjacent strip plates.
摘要翻译：本发明提出一种带状板结构及其制造方法。在一个实施例中，带状板结构包括带板阵列，其包括以预定方向排列的多个带状板，每个带状板包括面向带状板结构的一个侧面方向的第一表面和面向所述带状板结构的基本相反的侧面方向; 以及多个条状片，每个条带交替地邻接两个相邻带状板的第一表面或第二表面。

79. 发明申请

US20120168823A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120168823A1
公开(公告)日：2012-07-05
申请号：US13377766
申请日：2011-04-25
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/26 , H01L21/66
CPC分类号： H01L21/823807 , H01L21/02639 , H01L21/02647 , H01L21/76224 , H01L21/76229 , H01L21/823878 , H01L21/8258 , H01L29/66477
摘要： The present application discloses a semiconductor device and a method for forming the same. The method comprises: providing a first semiconductor layer and forming a first STI in the first semiconductor layer; determining a selected region in the first semiconductor layer, and making a portion of the first semiconductor layer in the selected region recessed; and in the selected region, epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the material of the second semiconductor layer is different from that of the first semiconductor layer. According to the present invention, a structure with a second semiconductor layer selectively epitaxially grown and embedded in the first semiconductor layer can be formed by a simple process, and defects generated during the epitaxial growth process can be further reduced.
摘要翻译：本申请公开了一种半导体器件及其形成方法。该方法包括：提供第一半导体层并在第一半导体层中形成第一STI; 确定所述第一半导体层中的选定区域，以及使所述选定区域中的所述第一半导体层的一部分凹陷; 并且在所选择的区域中，在第一半导体层上外延生长第二半导体层，其中第二半导体层的材料与第一半导体层的材料不同。根据本发明，可以通过简单的工艺形成具有选择性地外延生长并嵌入第一半导体层中的第二半导体层的结构，并且可以进一步减少在外延生长工艺期间产生的缺陷。

80. 发明申请

US20120038006A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120038006A1
公开(公告)日：2012-02-16
申请号：US12937652
申请日：2010-07-25
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qiagqing Liang
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo , Qiagqing Liang
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/66795 , H01L29/66803 , H01L29/7848 , H01L29/785
摘要： The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer. The semiconductor device has an improved short channel effect and a reduced parasitic capacitance and resistance, which contributes to an improved electrical property and facilitates scaling down of the transistor.
摘要翻译：本申请公开了一种半导体器件，其包括由半导体衬底上的半导体层形成并具有垂直于半导体衬底的主表面的两个相对侧的半导体材料的鳍; 源极区域和漏极区域，设置在所述半导体衬底中，邻近所述鳍片的两端并被所述鳍片桥接; 设置在所述翅片的中央部的通道区域; 以及设置在鳍的一侧的栅极电介质和栅极导体的堆叠，其中栅极导体通过栅极电介质与沟道区隔离，并且其中栅极电介质和栅极导体的堆叠远离翅片在平行于半导体衬底的主表面的方向上，并且通过绝缘层与半导体衬底绝缘。半导体器件具有改善的短沟道效应和减小的寄生电容和电阻，这有助于改善电性能并且有助于晶体管的缩小。

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