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    • 72. 发明授权
    • Method of manufacturing dual damascene structure
    • 双镶嵌结构的制造方法
    • US06403469B1
    • 2002-06-11
    • US09660071
    • 2000-09-12
    • Teng-Chun TsaiHsueh-Chung ChenMing-Sheng Yang
    • Teng-Chun TsaiHsueh-Chung ChenMing-Sheng Yang
    • H01L214763
    • H01L21/7684
    • A method of producing a dual damascene structure. A substrate is provided and an insulation layer is formed over the substrate. A dual damascene opening is formed in the insulation layer. A liner layer is formed over the exposed surface of the dual damascene opening. Metallic material is deposited over the substrate filling the dual damascene opening to form a metallic layer. A cap layer is formed over the metallic layer. A chemical-mechanical polishing operation is carried out to polish the cap layer using a metal-reactive solution or a cap-layer-reactive solution. The polishing operation continues until the cap layer outside the dual damascene opening is completely removed and the metallic layer is exposed. A portion of the cap layer remains above the dual damascene opening. Using the retained cap layer as a protective layer for the metallic layer, the metallic layer outside the dual damascene opening is removed by polishing until the liner layer is exposed. Lastly, the liner layer is removed to form a slightly protruding metal line structure.
    • 一种制造双镶嵌结构的方法。 提供衬底并且在衬底上形成绝缘层。 在绝缘层中形成双镶嵌开口。 在双镶嵌开口的暴露表面上形成衬里层。 金属材料沉积在填充双镶嵌开口的基底上以形成金属层。 在金属层上形成覆盖层。 进行化学机械抛光操作以使用金属反应性溶液或盖层反应性溶液来抛光盖层。 抛光操作继续,直到双镶嵌开口外的盖层被完全去除并且金属层被暴露。 盖层的一部分保留在双镶嵌开口的上方。 使用保留的盖层作为金属层的保护层,通过抛光除去双镶嵌开口外侧的金属层直到衬里层露出。 最后,去除衬里层以形成稍微突出的金属线结构。
    • 73. 发明授权
    • Dual damascene CMP process with BPSG reflowed contact hole
    • 双镶嵌CMP工艺与BPSG回流接触孔
    • US06239017B1
    • 2001-05-29
    • US09156357
    • 1998-09-18
    • Chine-Gie LouHsueh-Chung Chen
    • Chine-Gie LouHsueh-Chung Chen
    • H01L214763
    • H01L21/76828H01L21/31612H01L21/31625H01L21/76804H01L21/76807H01L2221/1036
    • An improved and new process for fabricating a planarized dual damascene contact hole and trench structure, wherein the contact holes have tapered sidewalls, has been developed. The dual damascene contact hole and trench are formed in a three layer insulator structure, in which the middle layer is a doped silicon oxide having a lower reflow temperature than the undoped silicon oxide layers forming the top and bottom layers. The contact holes are etched through the doped silicon oxide layer and the bottom undoped silicon oxide layer. The trenches are etched through the top undoped silicon oxide layer. After etching tapered sidewalls are formed at the contact holes by reflow of the doped silicon oxide through which the holes are etched.
    • 已经开发了一种用于制造平面化双镶嵌接触孔和沟槽结构的改进和新工艺,其中接触孔具有锥形侧壁。 双镶嵌接触孔和沟槽形成为三层绝缘体结构,其中中间层是具有比形成顶层和底层的未掺杂氧化硅层低的回流温度的掺杂氧化硅。 通过掺杂氧化硅层和底部未掺杂的氧化硅层蚀刻接触孔。 通过顶部未掺杂的氧化硅层蚀刻沟槽。 蚀刻之后,通过掺杂氧化硅的回流在接触孔处形成锥形侧壁,通过该掺杂氧化硅蚀刻孔。
    • 74. 发明授权
    • Method of fabricating shallow trench isolation
    • 浅沟槽隔离的制作方法
    • US06238997B1
    • 2001-05-29
    • US09237162
    • 1999-01-25
    • Hsueh-Chung ChenChien-Hung Chen
    • Hsueh-Chung ChenChien-Hung Chen
    • H01L2176
    • H01L21/76229
    • A method of fabricating a shallow trench isolation. A pad oxide layer, a mask layer, an oxide layer, and a polysilicon layer are formed over a substrate. A trench is formed in order to define active regions of the substrate. An oxide layer is filled in the trenches. There is a high etching selectivity for etching the oxide layer and the polysilicon layer. Thus, the polysilicon layer can be used as an etching stop layer. The polishing etching rates of the polysilicon layer and the silicon oxide layer are close during a chemical-mechanical polishing process. In this manner, a smooth surface over the active regions can be formed. Polishing and etching processes are performed in order to form a shallow trench isolation.
    • 制造浅沟槽隔离的方法。 在衬底上形成衬垫氧化物层,掩模层,氧化物层和多晶硅层。 形成沟槽以便限定衬底的有源区。 氧化层填充在沟槽中。 蚀刻氧化物层和多晶硅层的蚀刻选择性高。 因此,多晶硅层可以用作蚀刻停止层。 在化学机械抛光过程中,多晶硅层和氧化硅层的抛光蚀刻速率接近。 以这种方式,可以形成活性区域上的平滑表面。 进行抛光和蚀刻工艺以形成浅沟槽隔离。
    • 76. 发明授权
    • Physical vapor deposition device for forming a uniform metal layer on a
semiconductor wafer
    • 用于在半导体晶片上形成均匀金属层的物理气相沉积装置
    • US6099705A
    • 2000-08-08
    • US391323
    • 1999-09-08
    • Hsueh-Chung ChenJuan-Yuan WuWater Lur
    • Hsueh-Chung ChenJuan-Yuan WuWater Lur
    • C23C14/35C23C14/38C23C14/40C23C14/42C23C14/44
    • C23C14/35
    • A physical vapor deposition device comprises a vacuum chamber in which Ar ions are generated, a wafer chuck for holding a circular-shaped semiconductor wafer, a circular-shaped metal target above the wafer, an annular metal coil between the metal target and the wafer and made of the same material as the metal target, and a voltage controller for supplying voltage to the metal target, the wafer chuck and the metal coil. During a PVD processing, the voltage controller generates voltage biases between the metal target and the wafer chuck and between the metal coil and wafer chuck. That causes Ar ions to bombard the metal target to release metal atoms sputtering onto the center portion of the wafer, and causes Ar ions to bombard the metal coil to release the metal atoms sputtering onto the peripheral portion of the wafer so as to create a uniform metal layer on the wafer.
    • 物理气相沉积装置包括其中产生Ar离子的真空室,用于保持圆形半导体晶片的晶片卡盘,晶片上方的圆形金属靶,金属靶和晶片之间的环形金属线圈,以及 由与金属靶相同的材料制成,以及用于向金属靶,晶片卡盘和金属线圈提供电压的电压控制器。 在PVD处理期间,电压控制器在金属靶和晶片卡盘之间以及金属线圈和晶片卡盘之间产生电压偏压。 这导致Ar离子轰击金属靶,释放金属原子溅射到晶片的中心部分,并导致Ar离子轰击金属线圈,以将金属原子溅射到晶片的周边部分,从而形成均匀的 晶圆上的金属层。