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71. 发明申请

US20120023285A1 NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION 有权
标题翻译：具有动态多模式操作的非易失性存储器
公开(公告)号：US20120023285A1
公开(公告)日：2012-01-26
申请号：US13239813
申请日：2011-09-22
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G06F12/02
CPC分类号： G11C16/06 , G06F12/0246 , G06F2212/7204 , G06F2212/7206 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C2211/5641 , G11C2211/5646
摘要： A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.
摘要翻译：一种用于延长闪存设备的使用寿命的方法和系统。闪速存储器件是可动态配置的，以每单元单位（SBC）存储模式或每位单元（MBC）模式存储数据，使得两个SBC数据和MBC数据共存在同一存储器阵列中。存储在每个存储器页面中的一个或多个标签位用于指示用于将数据存储在相应细分中的存储模式的类型，其中细分可以是存储体，块或页面。控制器监视对应于每个页面的编程擦除周期的数量，以选择性地改变存储模式，以便最大化多模式闪存设备的任何细分的寿命。

72. 发明申请

US20110242906A1 DUAL FUNCTION COMPATIBLE NON-VOLATILE MEMORY DEVICE 有权
标题翻译：双功能兼容的非易失性存储器件
公开(公告)号：US20110242906A1
公开(公告)日：2011-10-06
申请号：US13159060
申请日：2011-06-13
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C16/06 , G11C5/14 , G11C5/143 , G11C7/20 , G11C16/20
摘要： A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.
摘要翻译：兼容异步操作和同步串行操作的双功能存储器件架构。双功能存储设备架构包括具有两个不同功能分配的一组物理端口。存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

73. 发明申请

US20110170352A1 NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES 有权
标题翻译：具有多个单元基板的NAND闪存
公开(公告)号：US20110170352A1
公开(公告)日：2011-07-14
申请号：US13073150
申请日：2011-03-28
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/02
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11524
摘要： A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
摘要翻译：具有连接到页缓冲器的存储器阵列的多个位线的NAND闪存库，其中连接到相同位线的NAND单元串形成在至少两个阱扇区中。在擦除操作期间，至少一个阱区可以选择性地耦合到擦除电压，使得未选择的阱区被禁止接收擦除电压。当井区的面积减小时，每个井区的电容相应减小。因此，当电荷泵电路驱动能力保持不变时，可以获得NAND闪速存储单元相对于单个存储器组的更高速擦除。或者，通过将具有特定面积的阱段与具有降低的驱动能力的电荷泵相匹配来获得对应于单阱存储器组的恒定擦除速度。降低的驱动电容电荷泵将占用较少的半导体芯片面积，从而降低成本。

74. 发明申请

US20100214812A1 STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE 有权
标题翻译：堆叠的半导体器件，包括主器件
公开(公告)号：US20100214812A1
公开(公告)日：2010-08-26
申请号：US12429310
申请日：2009-04-24
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C5/02 , H01L21/00
CPC分类号： G11C5/063 , G11C5/02 , G11C5/06 , G11C16/30 , H01L21/50 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).
摘要翻译：公开了一种包括非易失性存储器件的堆叠。堆栈中的非易失性存储器件之一是主器件，而其余存储器件或器件是从器件。

75. 发明申请

US20100174854A1 NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION 有权
标题翻译：具有动态多模式操作的非易失性存储器
公开(公告)号：US20100174854A1
公开(公告)日：2010-07-08
申请号：US12635280
申请日：2009-12-10
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G06F12/02 , G06F12/10 , G06F12/08 , G06F12/14
CPC分类号： G11C16/06 , G06F12/0246 , G06F2212/7204 , G06F2212/7206 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C2211/5641 , G11C2211/5646
摘要： A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device.
摘要翻译：一种用于延长闪存设备的使用寿命的方法和系统。闪速存储器件是可动态配置的，以每单元单位（SBC）存储模式或每位单元（MBC）模式存储数据，使得两个SBC数据和MBC数据共存在同一存储器阵列中。存储在每个存储器页面中的一个或多个标签位用于指示用于将数据存储在相应细分中的存储模式的类型，其中细分可以是存储体，块或页面。控制器监视对应于每个页面的编程擦除周期的数量，以选择性地改变存储模式，以便最大化多模式闪存设备的任何细分的寿命。

76. 发明申请

US20100091536A1 COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM 有权
标题翻译：具有用于将分离存储器件连接到系统的桥接装置的复合存储器
公开(公告)号：US20100091536A1
公开(公告)日：2010-04-15
申请号：US12401963
申请日：2009-03-11
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C7/00 , G11C5/02 , G11C5/025
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.
摘要翻译：一种复合存储器件，包括分立存储器件和用于响应具有与存储器件不兼容的格式或协议的全局存储器控制信号来控制分立存储器件的桥接器件。分立存储器件可以是对现有或本地存储器控制信号进行响应的商业现成存储器件或定制存储器件。全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。复合存储器件包括包括分立存储器件和桥接器件的半导体管芯的封装的系统，或者可以包括具有封装的分立存储器件的印刷电路板和安装在其上的封装桥接器件。

77. 发明申请

US20090175081A1 NAND FLASH MEMORY HAVING MULTIPLE CELL SUBSTRATES 有权
标题翻译：具有多个单元基板的NAND闪存
公开(公告)号：US20090175081A1
公开(公告)日：2009-07-09
申请号：US12143285
申请日：2008-06-20
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/06
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11524
摘要： A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
摘要翻译：具有连接到页缓冲器的存储器阵列的多个位线的NAND闪存库，其中连接到相同位线的NAND单元串形成在至少两个阱扇区中。在擦除操作期间，至少一个阱区可以选择性地耦合到擦除电压，使得未选择的阱区被禁止接收擦除电压。当井区的面积减小时，每个井区的电容相应减小。因此，当电荷泵电路驱动能力保持不变时，可以获得NAND闪速存储单元相对于单个存储器组的更高速擦除。或者，通过将具有特定面积的阱段与具有降低的驱动能力的电荷泵相匹配来获得对应于单阱存储器组的恒定擦除速度。降低的驱动电容电荷泵将占用较少的半导体芯片面积，从而降低成本。

78. 发明申请

US20080123423A1 NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE 有权
标题翻译：非易失性存储器串行核心架构
公开(公告)号：US20080123423A1
公开(公告)日：2008-05-29
申请号：US11944535
申请日：2007-11-23
申请人： Jin-Ki KIM
发明人： Jin-Ki KIM
IPC分类号： G11C16/04 , G11C7/00 , G11C8/00
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0659 , G06F3/0679 , G11C5/025 , G11C7/1006 , G11C7/1033 , G11C7/1039 , G11C7/1042 , G11C7/1048 , G11C7/1051 , G11C7/1072 , G11C7/12 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , G11C16/26 , G11C16/32 , G11C2207/107 , G11C2216/14 , G11C2216/20 , G11C2216/30
摘要： A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.
摘要翻译：一种具有串行数据接口和串行数据路径核心的存储器系统，用于从至少一个存储器组接收数据并将数据作为串行比特流提供给至少一个存储体。记忆库分为两半，每半部分分为上下扇区。每个扇区使用集成的自列解码电路并行提供与共享的二维页面缓冲器的数据。存储器中的串行到并行数据转换器将并行数据从一半耦合到串行数据路径核心。具有集成自列解码电路的共享二维页面缓冲器最小化每个存储体的电路和芯片面积开销，并且串行数据路径核心减少通常用于布线宽数据总线的芯片面积。因此，与具有相同密度的单个存储体系统相比，实现多存储体系统而没有显着相应的芯片面积增加。

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