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71. 发明授权

US06197635B1 Method of manufacturing a semiconductor device with reduced masking and without ARC loss in peripheral circuitry region 有权
标题翻译：制造半导体器件的方法，该半导体器件在外围电路区域中具有减小的掩蔽并且没有ARC损耗
公开(公告)号：US06197635B1
公开(公告)日：2001-03-06
申请号：US09417130
申请日：1999-10-13
申请人： Tommy C. Hsaio , Mark T. Ramsbey , Yu Sun
发明人： Tommy C. Hsaio , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Processing is simplified by employing the same mask in the memory cell region for patterning the stacked gate electrode structure and for ion implanting the shallow source/drain extensions. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.
摘要翻译：半导体器件的外围电路区域中的栅电极结构的改进的尺寸精度通过在图案化和离子注入期间避免与芯存储器单元区域中的多个掩模相关联的光致抗蚀剂剥离期间的ARC损耗来实现。通过在存储单元区域中采用相同的掩模来简化处理，用于图案化堆叠的栅电极结构和用于离子注入浅源/漏扩展。实施例包括初始蚀刻以在外围电路区域中形成栅电极结构。随后，通过蚀刻堆叠的栅极电极结构和离子注入来进行核心存储单元区域中的处理，以形成具有光刻胶层的伴随剥离的源极/漏极。

72. 发明授权

US6001713A Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device 有权
标题翻译：在非易失性半导体存储器件中的浮栅和互聚电介质层中形成富氮区的方法
公开(公告)号：US6001713A
公开(公告)日：1999-12-14
申请号：US154074
申请日：1998-09-16
申请人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
发明人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
IPC分类号： H01L21/28 , H01L21/265
CPC分类号： H01L21/28273
摘要： Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.
摘要翻译：提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。这在浮动栅极内形成初始氮浓度分布。然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

73. 发明授权

US5933730A Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method 失效
标题翻译：形成自对准源之后的间隔物形成和源保护的方法以及通过这种方法提供的装置
公开(公告)号：US5933730A
公开(公告)日：1999-08-03
申请号：US813562
申请日：1997-03-07
申请人： Yu Sun , Chi Chang , Mark T. Ramsbey
发明人： Yu Sun , Chi Chang , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.
摘要翻译：本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

74. 发明授权

US5899726A Method of forming oxide isolation in a semiconductor device 失效
标题翻译：在半导体器件中形成氧化物隔离的方法
公开(公告)号：US5899726A
公开(公告)日：1999-05-04
申请号：US891920
申请日：1997-07-14
申请人： Hsingya Arthur Wang , Mark T. Ramsbey , Jein-Chen Young
发明人： Hsingya Arthur Wang , Mark T. Ramsbey , Jein-Chen Young
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： After providing a patterned nitride layer over a patterned layer of oxide in turn disposed on a silicon substrate, a covering layer of oxide or polysilicon is deposited over the resulting structure to contact the substrate to hold the patterned nitride layer portions in position as field oxide is grown. In addition, field oxide growth rate slows at the edges of the nitride layer portions, allowing additional time for field oxide to flow as it is grown, relieving lifting force on the nitride layer portions, and providing an increase in silicon active area between field oxide regions.
摘要翻译：在依次设置在硅衬底上的图案化氧化物层上提供图案化氮化物层之后，在所得结构上沉积氧化物或多晶硅的覆盖层以接触衬底以将图案化的氮化物层部分保持在适当位置，因为场氧化物长大的。此外，场氧化物生长速率在氮化物层部分的边缘处减慢，允许场氧化物在其生长时流动的额外时间，减轻氮化物层部分上的提升力，并且提供场氧化物之间的硅有源面积的增加地区。

75. 发明授权

US5747882A Device including means for preventing tungsten silicide lifting, and method of fabrication thereof 失效
标题翻译：包括防止硅化钨提升的装置的装置及其制造方法
公开(公告)号：US5747882A
公开(公告)日：1998-05-05
申请号：US744962
申请日：1996-11-07
申请人： Hsingya Arthur Wang , Mark T. Ramsbey , Yu Sun
发明人： Hsingya Arthur Wang , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L29/49 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L29/4933
摘要： In a semiconductor device, a layer of nitrogen doped polysilicon is applied to a gate oxide in turn provided on a semiconductor body, and then a silicide film is applied to the polysilicon layer. The nitrogen in the polysilicon layer inhibits growth of native oxide on the polysilicon layer prior to the application of silicide, and at subsequent high temperature processing steps, so that the problem of the silicide layer lifting from the polysilicon layer due to this native oxide growth is avoided during subsequent high temperature processing of the device.
摘要翻译：在半导体器件中，将氮掺杂多晶硅层依次设置在半导体本体上，然后将硅化物膜施加到多晶硅层。多晶硅层中的氮在施加硅化物之前抑制多晶硅层上的自然氧化物的生长，并且在随后的高温处理步骤中，使得由于该自然氧化物生长而导致从多晶硅层提升的硅化物层的问题是在设备的后续高温处理期间避免。

76. 发明授权

US08957472B2 Memory device having trapezoidal bitlines and method of fabricating same 有权
标题翻译：具有梯形位线的存储器件及其制造方法
公开(公告)号：US08957472B2
公开(公告)日：2015-02-17
申请号：US13357252
申请日：2012-01-24
申请人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。

77. 发明授权

US08125018B2 Memory device having trapezoidal bitlines and method of fabricating same 有权
标题翻译：具有梯形位线的存储器件及其制造方法
公开(公告)号：US08125018B2
公开(公告)日：2012-02-28
申请号：US11033588
申请日：2005-01-12
申请人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
发明人： Ashot Melik-Martirosian , Mark T. Ramsbey , Mark W. Randolph
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译：提供了存储器件和制造方法。存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。

78. 发明授权

US07964905B1 Anti-reflective interpoly dielectric 有权
标题翻译：防反射层间电介质
公开(公告)号：US07964905B1
公开(公告)日：2011-06-21
申请号：US09591266
申请日：2000-06-09
申请人： Robert B. Ogle, Jr. , Marina V. Plat , Mark T. Ramsbey
发明人： Robert B. Ogle, Jr. , Marina V. Plat , Mark T. Ramsbey
IPC分类号： H01L29/94
CPC分类号： H01L29/518 , H01L21/28273 , H01L29/42324 , H01L29/513
摘要： The invention provides core stacks for flash memory with an anti-reflective interpoly dielectric. Instead of requiring an anti-reflective coating at the top of the a stack, the present invention uses the interpoly layer as an anti-reflective coating in conjunction with a transmissive second polymer layer. Light is transmitted through the transmissive second polymer layer to the anti-reflective interpoly dielectric layer. The transmissive second polymer layer is formed from an amorphous silicon or polysilicon. Silicon oxynitride (SiON), as formed in the present invention, having a good dielectric constant K, is tailored in its index of refraction and in its thickness for utilization as both a good interpoly material and an anti-reflective coating.
摘要翻译：本发明提供了具有抗反射互聚电介质的闪存的核心堆叠。代替在堆叠的顶部需要抗反射涂层，本发明使用互聚层作为与透射性第二聚合物层结合的抗反射涂层。光通过透射的第二聚合物层传输到抗反射的多聚电介质层。透射的第二聚合物层由非晶硅或多晶硅形成。在本发明中形成的具有良好的介电常数K的氮氧化硅（SiON）在其折射率和其厚度方面被适应为良好的间隙材料和抗反射涂层。

79. 发明授权

US07256141B1 Interface layer between dual polycrystalline silicon layers 有权
标题翻译：双层多晶硅层之间的界面层
公开(公告)号：US07256141B1
公开(公告)日：2007-08-14
申请号：US11135492
申请日：2005-05-24
申请人： Mark T. Ramsbey , Weidong Qian , Mark Chang , Eric Paton
发明人： Mark T. Ramsbey , Weidong Qian , Mark Chang , Eric Paton
IPC分类号： H01L21/31
CPC分类号： H01L27/115 , H01L27/11568
摘要： A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.
摘要翻译： A结构接双晶硅层。该结构包括第一层多晶硅和形成在第一多晶硅层的表面上的金属界面层。该结构还包括形成在界面层的表面上的第二层多晶硅。

80. 发明授权

US07018868B1 Disposable hard mask for memory bitline scaling 有权
标题翻译：用于存储器位线缩放的一次性硬掩模
公开(公告)号：US07018868B1
公开(公告)日：2006-03-28
申请号：US10770245
申请日：2004-02-02
申请人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
发明人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
IPC分类号： H01L21/44
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和半导体器件的制造方法。半导体器件包括在半导体衬底中的掩埋位线。此外，掺杂区域形成在掩埋位线附近。与掩埋位线相邻的掺杂区域可以防止掩埋位线之间的漏电流。

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