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71. 发明授权

US10170409B2 Package on package architecture and method for making 有权
公开(公告)号：US10170409B2
公开(公告)日：2019-01-01
申请号：US15037276
申请日：2013-12-23
申请人： Sanka Ganesan , John S. Guzek , Nitesh Nimkar , Klaus Reingruber , Thorsten Meyer
发明人： Sanka Ganesan , John S. Guzek , Nitesh Nimkar , Klaus Reingruber , Thorsten Meyer
IPC分类号： H01L23/02 , H01L23/52 , H01L23/522 , H01L21/56 , H01L21/768 , H01L23/498 , H01L23/00 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/31 , H01L23/538
摘要： Embodiments of the present disclosure are directed to package assemblies and methods for fabricating package assemblies. In one embodiment, a package assembly includes a die at least partially embedded in a mold compound; and a through mold via (TMV). The TMV may have vertical sides or may include two different portions with varying shapes. In some instances, prefabricated via bars may be used during fabrication. Package assemblies of the present disclosure may include package-on-package (POP) interconnects having a pitch of less than 0.3 mm. Other embodiments may be described and/or claimed.

72. 发明授权

US09331057B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09331057B2
公开(公告)日：2016-05-03
申请号：US11924691
申请日：2007-10-26
申请人： Thorsten Meyer , Grit Sommer , Ralf Plieninger
发明人： Thorsten Meyer , Grit Sommer , Ralf Plieninger
IPC分类号： H01L21/20 , H01L25/16 , H01L23/522 , H01L23/64 , H01L23/00 , H01L25/00 , H01L49/02 , H01L21/56
CPC分类号： H01L25/16 , H01L21/568 , H01L23/5223 , H01L23/642 , H01L24/19 , H01L24/96 , H01L24/97 , H01L25/50 , H01L28/40 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13022 , H01L2224/20 , H01L2224/24195 , H01L2224/92 , H01L2224/97 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/30105 , H01L2224/96 , H01L2224/82
摘要： A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made of a conductive layer arranged over the semiconductor chip.
摘要翻译：公开了一种半导体器件。一个实施例提供一种半导体芯片。半导体芯片包括电容器的第一电极。绝缘层设置在第一电极的顶部。电容器的第二电极被施加在绝缘层上，其中第二电极由布置在半导体芯片上的导电层制成。

73. 发明授权

US09205868B2 Steering spindle arrangement 有权
标题翻译：转向主轴装置
公开(公告)号：US09205868B2
公开(公告)日：2015-12-08
申请号：US14237232
申请日：2012-08-03
申请人： Axel Hebenstreit , Hans-Dieter Loeffler , Thorsten Meyer
发明人： Axel Hebenstreit , Hans-Dieter Loeffler , Thorsten Meyer
IPC分类号： B62D1/16 , B62D7/06 , B62D1/20 , F16D1/08 , F16D3/38
CPC分类号： B62D7/06 , B62D1/20 , F16D1/0876 , F16D1/0882 , F16D1/0888 , F16D3/387
摘要： A steering spindle has a steering spindle connection connected to a fork crown of a steering coupling via an intermediate piece. The steering spindle connection and the intermediate piece are formed as plug partners at ends facing each other, by means of at least one tongue and groove guide element pair, which provides a torque-transmitting priority control. A groove and a tongue of the at least one tongue and groove guide element pair are positioned in the longitudinal axial direction on the steering spindle connection and the intermediate piece. The steering arrangement includes a clamping device that clamps the plug partners to each other in a plugging position.
摘要翻译：转向主轴具有通过中间件连接到转向联轴器的叉头的转向主轴连接。转向主轴连接件和中间件通过至少一个榫舌和槽导向元件对形成为彼此面对的端部处的插塞配合，其提供扭矩传递优先级控制。所述至少一个舌槽导向元件对的槽和舌部沿着纵向轴向位于转向主轴连接件和中间件上。该转向装置包括夹紧装置，该夹紧装置将插塞合体彼此夹持在堵塞位置。

74. 发明授权

US09126622B2 Steering arrangement 有权
标题翻译：指导安排
公开(公告)号：US09126622B2
公开(公告)日：2015-09-08
申请号：US14237289
申请日：2012-08-03
申请人： Axel Hebenstreit , Hans-Dieter Loeffler , Thorsten Meyer
发明人： Axel Hebenstreit , Hans-Dieter Loeffler , Thorsten Meyer
IPC分类号： B62D1/16 , B62D1/20 , F16D1/08 , F16D3/38 , F16D1/06
CPC分类号： B62D1/16 , B62D1/20 , F16D1/06 , F16D1/0876 , F16D1/0882 , F16D1/0888 , F16D3/387 , Y10T403/7026
摘要： A steering arrangement includes a steering spindle and a steering coupling provided with a fork crown bearing a connecting element that connects an end of the steering spindle to the steering coupling in the form of a plug connection. To enable the combined steering spindle and steering coupling ends to be connected to each other in the correct relative position and thus to be able to prevent a defective assembly, the steering spindle end and the connecting element are coaxial plug partners on ends facing each other, by means of at least one tongue and groove guide element pair that provides a torque-transmitting priority control. The at least one groove and/or the at least one tongue of the guide element pair is molded on the interior of the shaft. A clamping device clamps the plug partners against each other in a plugging position so that they cannot come loose.
摘要翻译：转向装置包括转向主轴和转向联轴器，该转向联轴器设置有叉形冠，其具有将转向主轴的端部与插头连接形式的转向联轴器连接的连接元件。为了使组合的转向主轴和转向联轴器端部能够以正确的相对位置彼此连接，并且因此能够防止组装不良，转向主轴端部和连接元件是彼此相对的端部上的同轴插头配件，通过提供转矩传递优先级控制的至少一个舌槽导向元件对。引导元件对的至少一个凹槽和/或至少一个舌片模制在轴的内部上。夹紧装置将插塞合体彼此夹紧在堵塞位置，使其不会松动。

75. 发明授权

US09093322B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09093322B2
公开(公告)日：2015-07-28
申请号：US11777694
申请日：2007-07-13
申请人： Thorsten Meyer , Markus Brunnbauer , Recai Sezi
发明人： Thorsten Meyer , Markus Brunnbauer , Recai Sezi
IPC分类号： H01L23/48 , H01L23/00 , B81C1/00 , H01L21/56 , H01L23/31
CPC分类号： H01L24/12 , B81B2207/07 , B81B2207/097 , B81C1/00301 , H01L21/568 , H01L23/3114 , H01L24/11 , H01L2224/02311 , H01L2224/0401 , H01L2224/05147 , H01L2224/05164 , H01L2224/05166 , H01L2224/05647 , H01L2224/1132 , H01L2224/1147 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2924/00014 , H01L2924/01074 , H01L2924/013
摘要： A semiconductor device is disclosed. One embodiment includes a semiconductor substrate and at least two insulating elements located above the semiconductor substrate or above a mold compound embedding the semiconductor substrate. The at least two insulating elements have a first face facing the semiconductor substrate or the mold compound and a second face facing away from the semiconductor substrate or the mold compound. A conductive element for each of the at least two insulating elements extends from the first face of the insulating element to the second face of the insulating element.
摘要翻译：公开了一种半导体器件。一个实施例包括半导体衬底和位于半导体衬底之上或在嵌入半导体衬底的模具化合物上方的至少两个绝缘元件。所述至少两个绝缘元件具有面对半导体衬底或模具化合物的第一面和背离半导体衬底或模具化合物的第二面。用于至少两个绝缘元件中的每一个的导电元件从绝缘元件的第一面延伸到绝缘元件的第二面。

76. 发明申请

US20140332937A1 WORKPIECE WITH SEMICONDUCTOR CHIPS, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A WORKPIECE WITH SEMICONDUCTOR CHIPS 审中-公开
标题翻译：具有半导体器件的半导体器件和半导体器件的制造方法以及用半导体器件制造工件的方法
公开(公告)号：US20140332937A1
公开(公告)日：2014-11-13
申请号：US14330066
申请日：2014-07-14
申请人： Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
发明人： Markus Brunnbauer , Thorsten Meyer , Stephan Bradl , Ralf Plieninger , Jens Pohl , Klaus Pressel , Recai Sezi
IPC分类号： H01L23/60 , H01L23/48
CPC分类号： H01L25/50 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L23/48 , H01L23/5389 , H01L23/552 , H01L23/60 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/97 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/1617 , H01L2924/181 , H01L2924/19043 , H01L2924/3025 , H01L2224/82 , H01L2924/00
摘要： A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
摘要翻译：工件具有至少两个半导体芯片，每个半导体芯片具有至少部分暴露的第一主表面和第二主表面。所述工件还包括布置在所述至少两个半导体芯片上的导电层，所述导电层至少布置在所述第二主表面的区域上，所述模制化合物布置在所述导电层上。

77. 发明授权

US08878335B2 Method and system for providing fusing after packaging of semiconductor devices 有权
标题翻译：用于在半导体器件封装之后提供熔化的方法和系统
公开(公告)号：US08878335B2
公开(公告)日：2014-11-04
申请号：US12977104
申请日：2010-12-23
申请人： Thorsten Meyer , Josef Boeck , Rudolf Lachner , Herbert Schaefer
发明人： Thorsten Meyer , Josef Boeck , Rudolf Lachner , Herbert Schaefer
IPC分类号： H01L29/00 , H01L23/525 , H01L21/66
CPC分类号： H01L23/5258 , H01L22/14 , H01L22/22 , H01L2924/0002 , H01L2924/014 , H01L2924/12044 , H01L2924/00
摘要： A method and a system for providing fusing after packaging of semiconductor devices are disclosed. In one embodiment, a semiconductor device is provided comprising a substrate comprising a fuse area, at least one fuse disposed in the fuse area, and at least one layer disposed over the substrate, wherein the at least one layer comprises at least one opening exposing the at least one fuse.
摘要翻译：公开了一种用于在半导体器件封装之后提供熔化的方法和系统。在一个实施例中，提供了一种半导体器件，其包括衬底，该衬底包括保险丝区域，设置在熔丝区域中的至少一个熔丝以及设置在衬底上的至少一个层，其中至少一个层包括至少一个露出至少有一个保险丝。

78. 发明申请

US20140264831A1 CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT 审中-公开
标题翻译：芯片布置和制造芯片布置方法
公开(公告)号：US20140264831A1
公开(公告)日：2014-09-18
申请号：US13802843
申请日：2013-03-14
申请人： Thorsten Meyer
发明人： Thorsten Meyer
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L25/0657 , H01L21/4846 , H01L21/56 , H01L21/563 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L23/49838 , H01L23/525 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/1703 , H01L2224/73209 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2924/12042 , H01L2924/1461 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/00 , H01L2224/81
摘要： A chip arrangement may include: a first semiconductor chip having a first side and a second side opposite the first side; a second semiconductor chip having a first side and a second side opposite the first side, the second semiconductor chip disposed at the first side of the first semiconductor chip and electrically coupled to the first semiconductor chip, the first side of the second semiconductor chip facing the first side of the first semiconductor chip; an encapsulation layer at least partially encapsulating the first semiconductor chip and the second semiconductor chip, the encapsulation layer having a first side and a second side opposite the first side, the second side facing in a same direction as the second side of the second semiconductor chip; and an interconnect structure disposed at least partially within the encapsulation layer and electrically coupled to at least one of the first and second semiconductor chips, wherein the interconnect structure may extend to the second side of the encapsulation layer.
摘要翻译：芯片布置可以包括：具有第一侧和与第一侧相对的第二侧的第一半导体芯片; 第二半导体芯片，具有与第一侧相对的第一侧和第二侧，第二半导体芯片设置在第一半导体芯片的第一侧并电耦合到第一半导体芯片，第二半导体芯片的第一侧面向第一半导体芯片第一半导体芯片的第一面; 至少部分地封装所述第一半导体芯片和所述第二半导体芯片的封装层，所述封装层具有与所述第一侧相对的第一侧和第二侧，所述第二侧面向与所述第二半导体芯片的所述第二侧相同的方向 ; 以及互连结构，其至少部分地设置在封装层内并电耦合到第一和第二半导体芯片中的至少一个，其中互连结构可以延伸到封装层的第二侧。

79. 发明申请

US20140264808A1 CHIP ARRANGEMENTS, CHIP PACKAGES, AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT 审中-公开
标题翻译：芯片安排，芯片包装和制造芯片布置的方法
公开(公告)号：US20140264808A1
公开(公告)日：2014-09-18
申请号：US13832200
申请日：2013-03-15
申请人： Andreas Wolter , Thorsten Meyer
发明人： Andreas Wolter , Thorsten Meyer
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L24/19 , B81B2207/07 , B81B2207/096 , B81C1/0023 , B81C2203/0792 , H01L23/055 , H01L23/3128 , H01L25/0657 , H01L25/16 , H01L2224/12105 , H01L2224/16145 , H01L2224/16225 , H01L2224/2518 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73259 , H01L2224/73265 , H01L2225/0651 , H01L2225/06548 , H01L2225/06572 , H01L2924/07802 , H01L2924/07811 , H01L2924/12042 , H01L2924/1461 , H01L2924/15153 , H01L2924/15311 , H01L2924/1815 , H01L2924/351 , H01L2924/00 , H01L2924/181
摘要： A chip arrangement may include a semiconductor chip; an encapsulation layer at least partially encapsulating the semiconductor chip, the encapsulation layer having a receiving region configured to receive an electronic device, the receiving region comprising a cavity; and an electronic device disposed in the receiving region.
摘要翻译：芯片布置可以包括半导体芯片; 至少部分地封装所述半导体芯片的封装层，所述封装层具有被配置为接收电子器件的接收区域，所述接收区域包括空腔; 以及设置在接收区域中的电子设备。

80. 发明申请

US20140206142A1 FLIP-CHIP WAFER LEVEL PACKAGE AND METHODS THEREOF 审中-公开
标题翻译： FLIP-CHIP WAFER LEVEL PACKAGE及其方法
公开(公告)号：US20140206142A1
公开(公告)日：2014-07-24
申请号：US14225647
申请日：2014-03-26
申请人： Thorsten Meyer
发明人： Thorsten Meyer
IPC分类号： H01L23/00
CPC分类号： H01L24/96 , H01L21/568 , H01L23/3128 , H01L23/49816 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/16 , H01L24/24 , H01L24/73 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L2224/16225 , H01L2224/16227 , H01L2224/24225 , H01L2224/2919 , H01L2224/32135 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/73267 , H01L2224/81005 , H01L2224/83005 , H01L2224/83862 , H01L2224/92225 , H01L2224/92244 , H01L2225/06517 , H01L2225/06524 , H01L2225/06558 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： An electronic package includes a flip-chip component having a first die coupled to a flip-chip substrate, second die stacked on the first die, an encapsulation compound formed around the first die and the second die, a set of through encapsulant vias (TEVs) providing a set of electrical connections from a first side of the electronic package to a second side of the electronic package through the encapsulation compound to the flip-chip substrate, and a redistribution layer electrically connecting a set of contacts on the second die to the set of TEVs on the first side of the electronic package.
摘要翻译：电子封装包括倒装芯片组件，其具有耦合到倒装芯片衬底的第一管芯，堆叠在第一管芯上的第二管芯，形成在第一管芯和第二管芯周围的封装化合物，一组通过封装通孔（TEV ）提供从电子封装的第一侧到电子封装的第二侧的一组电连接，通过封装化合物到倒装芯片衬底，以及再分配层，将第二裸片上的一组触点电连接到在电子包装的第一面设置一组TEV。

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