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71. 发明申请

US20130009244A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130009244A1
公开(公告)日：2013-01-10
申请号：US13379444
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/42384 , H01L29/78648
摘要： The present application discloses an MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first insulation buried layer disposed on the semiconductor substrate; a back gate formed in a first semiconductor layer which is disposed on the first insulation buried layer; a second insulation buried layer disposed on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is disposed on the second insulation buried layer; a gate disposed on the second semiconductor layer; and electric connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoins the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions. The MOSFET, of any conductivity type, can have adjustable threshold voltage and reduced leakage current via the back gate between the source/drain regions by using the back gate in the form of a PNP junction or an NPN junction.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 设置在所述半导体基板上的第一绝缘埋层; 形成在第一绝缘掩埋层上的第一半导体层中形成的背栅; 设置在所述第一半导体层上的第二绝缘埋层; 源极/漏极区域，形成在第二绝缘掩埋层上的第二半导体层中; 设置在所述第二半导体层上的栅极; 以及与源极/漏极区域，栅极和背栅极的电连接，其中所述背栅极包括设置在所述源极/漏极区域下方的第一导电类型的第一后栅极区域和具有第二导电性的第二背栅极区域所述第一导电类型与所述第二导电类型相反，并且与所述第二导电类型的电连接包括与所述第二导电类型之一接触的导电通孔，第一个后门区域。任何导电类型的MOSFET可以通过使用PNP结或NPN结形式的背栅，通过源极/漏极区之间的背栅极具有可调节的阈值电压和减小的漏电流。

72. 发明申请

US20130001555A1 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130001555A1
公开(公告)日：2013-01-03
申请号：US13380654
申请日：2011-04-18
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/28525 , H01L21/76805 , H01L21/823425 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/41725 , H01L29/41783 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: depositing an interlayer dielectric layer (105) on a semiconductor substrate (101) to cover a source/drain region (102) and a gate stack on the semiconductor substrate (101); etching the interlayer dielectric layer and the source/drain region, so as to form a contact hole (110) extending into the source/drain region; conformally forming an amorphous layer (111) on an exposed part of the source/drain region; forming a metal silicide layer (113) on a surface of the amorphous layer (111); and filling the contact hole (110) with a contact metal (114). Correspondingly, the present invention further provides a semiconductor structure. The present invention etches the source/drain region so that the exposed part comprises the bottom and a sidewall, thereby expanding the contact area between the contact metal in the contact hole and the source/drain region, and reducing the contact resistance. The present invention effectively eliminates EOR defects caused by the amorphous ion implantation by forming an amorphous substance by a selective deposition.
摘要翻译：本发明提供一种制造半导体结构的方法，包括以下步骤：在半导体衬底（101）上沉积层间绝缘层（105）以覆盖半导体衬底上的源极/漏极区域（102）和栅极堆叠（101）; 蚀刻层间电介质层和源极/漏极区，以形成延伸到源/漏区的接触孔（110）; 在源极/漏极区域的暴露部分上保形地形成非晶层（111）; 在所述非晶层（111）的表面上形成金属硅化物层（113）; 以及用接触金属（114）填充接触孔（110）。相应地，本发明还提供一种半导体结构。本发明蚀刻源极/漏极区域，使得暴露部分包括底部和侧壁，从而扩大接触孔中的接触金属与源极/漏极区域之间的接触面积，并降低接触电阻。本发明通过选择性沉积形成无定形物质来有效地消除由非晶离子注入引起的EOR缺陷。

73. 发明申请

US20120329228A1 METHOD FOR FORMING A STRAINED SEMICONDUCTOR CHANNEL 审中-公开
标题翻译：形成应变半导体通道的方法
公开(公告)号：US20120329228A1
公开(公告)日：2012-12-27
申请号：US13380019
申请日：2011-08-09
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/1054 , H01L29/66537 , H01L29/78
摘要： The invention relates to a method of forming a strained semiconductor channel. According to the invention, a strained channel is formed after the annealing of source/drain, by which it does not only avoid the strained semiconductor channel from being exposed to the high-temperature source/drain annealing process, but also avoid a loss of the semiconductor layer since it reduces the number of processing steps that the strained semiconductor channel has to experience. Besides, because the etching rate of the ion implantation region is significantly greater than the etching rate of the surrounding portion of the relaxed layer into which no ions are implanted, the etching depth can be easily controlled.
摘要翻译：本发明涉及形成应变半导体通道的方法。根据本发明，在源/漏退火之后形成应变通道，不仅避免了应变半导体通道暴露于高温源/漏退火工艺，而且避免了因为它减少了应变半导体通道必须经历的处理步骤的数量。此外，由于离子注入区域的蚀刻速率明显大于其中没有注入离子的松弛层的周围部分的蚀刻速率，因此可以容易地控制蚀刻深度。

74. 发明申请

US20120326155A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120326155A1
公开(公告)日：2012-12-27
申请号：US13376247
申请日：2011-08-02
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/84 , H01L21/823828 , H01L21/823878 , H01L27/1203 , H01L29/4908 , H01L29/78603 , H01L29/78612
摘要： The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET.
摘要翻译：本申请公开了一种半导体结构及其制造方法。半导体结构包括：SOI衬底和形成在SOI衬底上的MOSFET，其中SOI衬底以自顶向下的方式包括SOI层，第一掩埋绝缘体层，埋入半导体层，第二掩埋绝缘体层和半导体衬底，所述掩埋半导体层包括背栅区，所述背栅区包括掺杂有第一极性的掺杂剂的所述掩埋半导体层的一部分; MOSFET包括栅极堆叠和源极/漏极区，栅极堆叠形成在SOI层上，并且源极/漏极区域形成在栅极堆叠的相对侧的SOI层中; 并且所述背栅区域包括反掺杂区域，所述反掺杂区域与所述栅叠层自对准并且包括第二极性的掺杂剂，并且所述第二极性与所述第一极性相反。本公开的实施例可以用于调整MOSFET的阈值电压。

75. 发明申请

US20120313158A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120313158A1
公开(公告)日：2012-12-13
申请号：US13380666
申请日：2011-08-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/28 , H01L29/788 , H01L29/792 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/518 , H01L21/28194 , H01L21/28518 , H01L21/76805 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L29/4966 , H01L29/513 , H01L29/66545 , H01L29/78
摘要： The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate, forming sequentially a first high-k dielectric layer, an adjusting layer, a second high-k dielectric layer and a metal gate on the substrate, etching the first high-k dielectric layer, the adjusting layer, the second high-k dielectric layer and the metal gate to form a gate stack. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes to arrange an adjusting layer between two layers of high-k dielectric layer, which effectively avoids reaction of the adjusting layer with the metal gate because of their direct contact, so as to maintain the performance of semiconductor devices.
摘要翻译：本发明提供一种半导体结构及其制造方法。该方法包括：提供衬底，在衬底上依次形成第一高k电介质层，调整层，第二高k电介质层和金属栅极，蚀刻第一高k电介质层，调整层，第二高k电介质层和金属栅极形成栅叠层。因此，本发明还提供一种半导体结构。本发明提出在两个高k电介质层之间布置调整层，由于它们的直接接触，有效地避免了调节层与金属栅极的反应，从而保持了半导体器件的性能。

76. 发明申请

US20120313149A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20120313149A1
公开(公告)日：2012-12-13
申请号：US13380707
申请日：2011-08-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/28518 , H01L21/76814 , H01L21/76816 , H01L29/66545
摘要： The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises the following steps: providing a semiconductor substrate, forming sequentially a gate dielectric layer, a metal gate, a CMP stop layer, and a poly silicon layer on the semiconductor substrate; etching the gate dielectric layer, the metal gate, the CMP stop layer and the poly silicon layer to form a gate stack; forming a first interlayer dielectric layer on the semiconductor substrate to cover the gate stack on the semiconductor substrate and the portions on both sides of the gate stack; performing a planarization process, such that the CMP stop layer is exposed and flushed with the upper surface of the first interlayer dielectric layer. Accordingly, the present invention further provides a semiconductor structure. Through adding the CMP stop layer, the present invention is able to effectively shorten the height of a metal gate, thus effectively reduces the capacitance between the metal gate and contact regions, and therefore optimizes the subsequent process for etching through holes.
摘要翻译：本发明提供一种半导体结构及其制造方法。该方法包括以下步骤：提供半导体衬底，在半导体衬底上依次形成栅极电介质层，金属栅极，CMP阻挡层和多晶硅层; 蚀刻栅极电介质层，金属栅极，CMP停止层和多晶硅层以形成栅极叠层; 在所述半导体衬底上形成第一层间电介质层，以覆盖所述半导体衬底上的所述栅极堆叠以及所述栅极堆叠的两侧的所述部分; 执行平坦化处理，使得CMP停止层与第一层间电介质层的上表面曝光和冲洗。因此，本发明还提供一种半导体结构。通过添加CMP停止层，本发明能够有效地缩短金属栅极的高度，从而有效地降低金属栅极和接触区域之间的电容，并因此优化用于蚀刻通孔的后续工艺。

77. 发明申请

US20120302025A1 Method for Manufacturing a Semiconductor Structure 审中-公开
标题翻译：制造半导体结构的方法
公开(公告)号：US20120302025A1
公开(公告)日：2012-11-29
申请号：US13380517
申请日：2011-08-25
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/336
CPC分类号： H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： The present application provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate; forming a gate dielectric layer on the substrate; forming a dummy gate structure on the gate dielectric layer, wherein the dummy gate is formed from a polymer material; implanting dopants into portions of the substrates on opposite sides of the dummy gate structure to form source/drain regions; removing the dummy gate; annealing the source/drain regions to activate the dopants; and forming a metal gate. According to the present invention, it is proposed to manufacture a dummy gate structure with a polymer material, which significantly simplifies the subsequent etching process for removing the dummy gate structure and alleviates the etching difficulty accordingly.
摘要翻译：本申请提供了一种制造半导体结构的方法，其包括以下步骤：提供衬底; 在所述基板上形成栅介电层; 在所述栅极电介质层上形成虚拟栅极结构，其中所述虚拟栅极由聚合物材料形成; 在所述虚拟栅极结构的相对侧上将掺杂剂注入到所述衬底的部分中以形成源极/漏极区域; 去除虚拟门; 对源/漏区进行退火以激活掺杂剂; 并形成金属门。根据本发明，提出了制造具有聚合物材料的虚拟栅极结构，这显着简化了用于去除伪栅极结构的随后的蚀刻工艺，并相应地减轻了蚀刻难度。

78. 发明申请

US20120299089A1 Semiconductor Device and Method for Manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120299089A1
公开(公告)日：2012-11-29
申请号：US13377729
申请日：2011-08-09
申请人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
发明人： Zhijiong Luo , Haizhou Yin , Huilong Zhu
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/66621 , H01L21/26506 , H01L29/66583 , H01L29/66772
摘要： It is disclosed a semiconductor device and a method for manufacturing the same. One method comprises providing a semiconductor layer that is formed on an insulating layer; forming a mask pattern on the semiconductor layer, which exposes a portion of the semiconductor layer; removing the exposed portion of the semiconductor layer of a predetermined thickness, thereby forming a groove; forming a gate stack in the mask pattern and the groove; removing the mask pattern to expose a portion of sidewalls of the gate stack. The method not only meets the requirement for a precise thickness of the SOI, but also increases the thickness of the source/drain regions as compared to a device having a uniform SOI thickness at the gate stack, thereby facilitating a reduction of the parasitic resistance of the source/drain regions.
摘要翻译：公开了一种半导体器件及其制造方法。一种方法包括提供形成在绝缘层上的半导体层; 在所述半导体层上形成掩模图案，所述掩模图案暴露所述半导体层的一部分; 去除预定厚度的半导体层的暴露部分，从而形成凹槽; 在掩模图案和凹槽中形成栅极堆叠; 去除掩模图案以暴露栅极堆叠的侧壁的一部分。该方法不仅满足SOI的精确厚度的要求，而且与在栅堆叠处具有均匀的SOI厚度的器件相比，也增加了源极/漏极区的厚度，从而有助于降低寄生电阻源极/漏极区域。

79. 发明申请

US20120261772A1 Semiconductor Device and Method for Manufacturing the Same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20120261772A1
公开(公告)日：2012-10-18
申请号：US13378996
申请日：2011-08-09
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/28518 , H01L29/41783
摘要： A semiconductor device comprises a gate stack, a source region, a drain region, a contact plug and an interlayer dielectric, the gate stack being formed on a substrate, the source region and the drain region being located on opposite sides of the gate stack and embedded in the substrate, the contact plug being embedded in the interlayer dielectric, wherein the contact plug comprises a first portion which is in contact with the source region and/or drain region, the upper surface of the first portion is flushed with the upper surface of the gate stack, and the angle between a sidewall and a bottom surface of the first portion is less than 90°. There is also provided a method for manufacturing a semiconductor device. Not only the contact area between the first portion and the source region and/or the drain region can be increased, which facilitates reducing the contact resistance; but also the distance between the top of the first portion and the top of the gate stack can be increased, which facilitates reducing the possibility of short circuit between the first portion and the gate stack.
摘要翻译：半导体器件包括栅极堆叠，源极区域，漏极区域，接触插塞和层间电介质，栅极堆叠层形成在衬底上，源极区域和漏极区域位于栅极叠层的相对侧上，以及嵌入在基板中，接触插塞嵌入在层间电介质中，其中接触插塞包括与源区和/或漏区接触的第一部分，第一部分的上表面被上表面并且第一部分的侧壁和底表面之间的角度小于90°。还提供了一种制造半导体器件的方法。不仅可以增加第一部分和源极区域和/或漏极区域之间的接触面积，这有助于降低接触电阻; 而且可以增加第一部分的顶部和栅极堆叠的顶部之间的距离，这有助于降低第一部分和栅极堆叠之间的短路的可能性。

80. 发明申请

US20120235213A1 SEMICONDUCTOR STRUCTURE WITH A STRESSED LAYER IN THE CHANNEL AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：在通道中具有受压层的半导体结构及其形成方法
公开(公告)号：US20120235213A1
公开(公告)日：2012-09-20
申请号：US12996673
申请日：2010-06-24
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26506 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7849
摘要： The present invention provides a semiconductor structure with a stressed layer in the channel and method for forming the same. The semiconductor structure comprises a substrate; a gate stack, including a gate dielectric layer formed over the substrate, gate layer formed over the gate dielectric layer, a source region and a drain region formed in the substrate by both sides of the gate stack; one or more spacers formed on both sides of the gate stack; and an embedded stressed layer formed under the gate stack in the substrate. In the embodiments of the present invention, the carrier mobility can be effectively increased by the embedded stressed layer added in the channel under the gate stack, so that the driving current of transistors is improved. Moreover, the technological process for forming this embedded stressed layer in the present invention has a lower thermal budget, which therefore assists in maintaining a higher stress level in the channel region. Besides, apart from the advantage in the aspect of stress, the embedded stressed layer in the channel can further decrease the diffusion/invasion of B (boron) from the heavily doped source and drain regions.
摘要翻译：本发明提供了一种在通道中具有应力层的半导体结构及其形成方法。半导体结构包括衬底; 包括形成在所述衬底上的栅极电介质层，形成在所述栅极介电层上的栅极层，由所述栅极堆叠的两侧形成在所述衬底中的源极区域和漏极区域的栅极堆叠; 形成在栅叠层两侧的一个或多个间隔物; 以及在衬底下形成在栅叠层下方的嵌入应力层。在本发明的实施例中，通过在栅堆叠下方的沟道中添加的嵌入的应力层可以有效地增加载流子迁移率，从而提高晶体管的驱动电流。此外，在本发明中形成该嵌入应力层的工艺过程具有较低的热量预算，因此有助于在沟道区域中保持更高的应力水平。此外，除了应力方面的优点之外，通道中的嵌入式应力层可以进一步降低来自重掺杂源极和漏极区的B（硼）的扩散/侵入。

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