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71. 发明授权

US07274072B2 Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance 有权
标题翻译：用于改善电池稳定性和性能的混合体SOI-6T-SRAM电池
公开(公告)号：US07274072B2
公开(公告)日：2007-09-25
申请号：US11108012
申请日：2005-04-15
申请人： Leland Chang , Shreesh Narasimha , Norman J. Rohrer , Jeffrey W. Sleight
发明人： Leland Chang , Shreesh Narasimha , Norman J. Rohrer , Jeffrey W. Sleight
IPC分类号： H01L29/72
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L27/1207
摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.
摘要翻译：本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

72. 发明申请

US20070106968A1 OPC TRIMMING FOR PERFORMANCE 失效
公开(公告)号：US20070106968A1
公开(公告)日：2007-05-10
申请号：US11164044
申请日：2005-11-08
申请人： James Culp , Lars Liebmann , Rajeev Malik , K. Paul Muller , Shreesh Narasimha , Stephen Runyon , Patrick Williams
发明人： James Culp , Lars Liebmann , Rajeev Malik , K. Paul Muller , Shreesh Narasimha , Stephen Runyon , Patrick Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.
摘要翻译：基于使用光学邻近校正技术的方法，在制造芯片之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。标记形状识别构成关键定时路径中的装置的电路的预定子组。根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。使用OPC技术为所选的关键设备制作掩码。

73. 发明授权

US07189644B2 CMOS device integration for low external resistance 有权
标题翻译： CMOS器件集成低外部电阻
公开(公告)号：US07189644B2
公开(公告)日：2007-03-13
申请号：US10763308
申请日：2004-01-23
申请人： Shreesh Narasimha , Patricia A. O'Neil
发明人： Shreesh Narasimha , Patricia A. O'Neil
IPC分类号： H01L21/4763 , H01L29/76
CPC分类号： H01L29/66507 , H01L29/665 , H01L29/6656
摘要： The present invention relates to a Complementary Metal Oxide Semiconductor (CMOS) device having a lower external resistance and a method for manufacturing the CMOS device. The inventive MOSFET is produced by forming first suicide regions in a substrate as well as atop surface of a gate region and forming second silicide regions where second silicide thickness is greater than the first silicide thickness. The inventive method produces a low resistance first silicide in close proximity to the channel region of the device, where the incorporation of the first silicide decreases the external resistance of the device while the incorporation of the second silicide produces low sheet resistance interconnects.
摘要翻译：本发明涉及具有较低外部电阻的互补金属氧化物半导体（CMOS）器件及其制造方法。本发明的MOSFET通过在衬底以及栅极区域的顶表面上形成第一硅化物区域并形成其中第二硅化物厚度大于第一硅化物厚度的第二硅化物区域来制造。本发明的方法在器件的沟道区域附近产生低电阻的第一硅化物，其中掺入第一硅化物降低了器件的外部电阻，同时掺入第二硅化物产生低的薄层电阻互连。

74. 发明申请

US20060231899A1 Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance 有权
标题翻译：用于改善电池稳定性和性能的混合体SOI-6T-SRAM电池
公开(公告)号：US20060231899A1
公开(公告)日：2006-10-19
申请号：US11108012
申请日：2005-04-15
申请人： Leland Chang , Shreesh Narasimha , Norman Rohrer , Jeffrey Sleight
发明人： Leland Chang , Shreesh Narasimha , Norman Rohrer , Jeffrey Sleight
IPC分类号： H01L29/94
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L27/1207
摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.
摘要翻译：本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。

75. 发明授权

US07071072B2 Forming shallow trench isolation without the use of CMP 失效
标题翻译：形成浅沟槽隔离而不使用CMP
公开(公告)号：US07071072B2
公开(公告)日：2006-07-04
申请号：US10710001
申请日：2004-06-11
申请人： Renee T. Mo , Shreesh Narasimha
发明人： Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/76
CPC分类号： H01L21/76283
摘要： Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch.
摘要翻译：通过沉积厚衬垫氮化物和沉积氧化物沟槽填充材料形成浅沟槽隔离结构，使得：a）沟槽中的材料在硅表面之上，具有允许在随后的前端去除沟槽填充的工艺余量使得最终沟槽填充水平基本上与硅共面; 和b）内壁上的氧化物容易去除，使得衬垫氮化物在湿蚀刻中被去除。

76. 发明申请

US20060128091A1 DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS 有权
标题翻译：具有增强应力状态的装置及相关方法
公开(公告)号：US20060128091A1
公开(公告)日：2006-06-15
申请号：US10905025
申请日：2004-12-10
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/66772 , Y10S438/938
摘要： The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.
摘要翻译：本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

77. 发明申请

US20060057797A1 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 失效
公开(公告)号：US20060057797A1
公开(公告)日：2006-03-16
申请号：US11266855
申请日：2005-11-04
申请人： Atul Ajmera , Andres Bryant , Percy Gilbert , Michael Gribelyuk , Edward Maciejewski , Renee Mo , Shreesh Narasimha
发明人： Atul Ajmera , Andres Bryant , Percy Gilbert , Michael Gribelyuk , Edward Maciejewski , Renee Mo , Shreesh Narasimha
IPC分类号： H01L21/8238
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

78. 发明授权

US06991979B2 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 有权
公开(公告)号：US06991979B2
公开(公告)日：2006-01-31
申请号：US10605311
申请日：2003-09-22
申请人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
发明人： Atul C. Ajmera , Andres Bryant , Percy V. Gilbert , Michael A Gribelyuk , Edward P. Maciejewski , Renee T. Mo , Shreesh Narasimha
IPC分类号： H01L21/8238
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

79. 发明申请

US20050277263A1 Forming Shallow Trench Isolation Without the Use of CMP 失效
标题翻译：形成浅沟槽隔离而不使用CMP
公开(公告)号：US20050277263A1
公开(公告)日：2005-12-15
申请号：US10710001
申请日：2004-06-11
申请人： Renee Mo , Shreesh Narasimha
发明人： Renee Mo , Shreesh Narasimha
IPC分类号： H01L21/331 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76283
摘要： Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch.
摘要翻译：通过沉积厚衬垫氮化物和沉积氧化物沟槽填充材料形成浅沟槽隔离结构，使得：a）沟槽中的材料在硅表面之上，具有允许在随后的前端去除沟槽填充的工艺余量使得最终沟槽填充水平基本上与硅共面; 和b）内壁上的氧化物容易去除，使得衬垫氮化物在湿蚀刻中被去除。

80. 发明授权

US09040399B2 Threshold voltage adjustment for thin body MOSFETs 有权
标题翻译：薄体MOSFET的阈值电压调整
公开(公告)号：US09040399B2
公开(公告)日：2015-05-26
申请号：US13282619
申请日：2011-10-27
申请人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
发明人： MaryJane Brodsky , Ming Cai , Dechao Guo , William K. Henson , Shreesh Narasimha , Yue Liang , Liyang Song , Yanfeng Wang , Chun-Chen Yeh
IPC分类号： H01L21/425 , H01L29/66
CPC分类号： H01L29/66803
摘要： A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.
摘要翻译：一种结构包括基板; 设置在所述衬底上的晶体管，所述晶体管包括由碳注入的由硅构成的鳍; 以及覆盖限定晶体管的沟道的鳍片的一部分上的栅极电介质层和栅极金属层。在该结构中，选择鳍内的碳浓度以建立晶体管的期望电压阈值。还公开了制造FinFET晶体管的方法。还公开了具有碳注入阱的平面晶体管，其中选择阱内的碳浓度以建立晶体管的期望电压阈值。

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