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71. 发明申请

US20090289291A1 SOI DEEP TRENCH CAPACITOR EMPLOYING A NON-CONFORMAL INNER SPACER 失效
标题翻译： SOI深层电容器采用不合格的内部间隔器
公开(公告)号：US20090289291A1
公开(公告)日：2009-11-26
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译：用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。或者，可以在形成掩埋带之前去除电介质间隔物。

72. 发明申请

US20090176339A1 Method of multi-port memory fabrication with parallel connected trench capacitors in a cell 失效
标题翻译：在单元中并联连接沟槽电容器的多端口存储器制造方法
公开(公告)号：US20090176339A1
公开(公告)日：2009-07-09
申请号：US12316748
申请日：2008-12-16
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage.
摘要翻译：提供了一种用于制造其中多个并联电容器在单元中的多端口存储器的方法。形成多个沟槽电容器，其具有沿多个沟槽的壁延伸的电容器电介质层，所述多个沟槽电容器具有第一电容器板和与第一电容器板相对的电容器电介质层的第二电容器板。第一电容器板导电地连接在一起，并且第二电容器板被导电地连接在一起。以这种方式，第一电容器板适于接收相同的可变电压，并且第二电容器板适于接收相同的固定电压。

73. 发明授权

US07550359B1 Methods involving silicon-on-insulator trench memory with implanted plate 有权
标题翻译：涉及具有植入板的绝缘体上硅沟槽存储器的方法
公开(公告)号：US07550359B1
公开(公告)日：2009-06-23
申请号：US12116626
申请日：2008-05-07
申请人： Kangguo Cheng , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions into the substrate and the SOI layer on a first opposing side of the trench and a second opposing side the trench to partially form a capacitor, depositing a node dielectric in the trench, filling the trench with a first polysilicon, removing a portion of the first polysilicon from the trench, removing an exposed portion of the node dielectric, filling the trench with a second polysilicon, masking to define an active region on the hardmask layer, forming shallow trench isolation (STI) such that the STI contacts a portion of the buried oxide layer, removing the hardmask layer, and forming a transistor.
摘要翻译：一种用于制造绝缘体上硅（SOI）沟槽存储器的方法，包括在衬底上形成沟槽，其中掩埋氧化物层设置在衬底上，SOI层设置在掩埋氧化物层上，并且设置硬掩模层在所述SOI层上，将离子注入到所述衬底中并且在所述沟槽的第一相对侧上的所述SOI层和所述沟槽的第二相对侧，以部分地形成电容器，在所述沟槽中沉积节点电介质，用第一多晶硅填充所述沟槽从所述沟槽去除所述第一多晶硅的一部分，去除所述节点电介质的暴露部分，用第二多晶硅填充所述沟槽，以掩蔽以限定所述硬掩模层上的有源区域，形成浅沟槽隔离（STI），使得 STI接触掩埋氧化物层的一部分，去除硬掩模层，并形成晶体管。

74. 发明申请

US20080124863A1 Trench Memory 有权
标题翻译：沟槽记忆
公开(公告)号：US20080124863A1
公开(公告)日：2008-05-29
申请号：US12023175
申请日：2008-01-31
申请人： Kangguo Cheng , Geng Wang
发明人： Kangguo Cheng , Geng Wang
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L27/10867
摘要： A trench device and method for fabricating same are provided. The trench device has a collar with a first portion that is doped and a second portion that is undoped. Fabrication of the partially doped collar can be done by deposition of a doped insulator in the trench, removal of a portion of the doped deposition, deposition of an undoped insulator in the trench and removal of a portion of the doped and undoped insulators.
摘要翻译：提供了一种沟槽器件及其制造方法。沟槽装置具有带有第一部分的套环，该第一部分被掺杂，而第二部分是未掺杂的。部分掺杂的环的制造可以通过在沟槽中沉积掺杂的绝缘体，去除掺杂沉积的一部分，在沟槽中沉积未掺杂的绝缘体以及去除掺杂和未掺杂的绝缘体的一部分来完成。

75. 发明申请

US20070189057A1 MULTIPLE PORT MEMORY HAVING A PLURALITY OF PARALLEL CONNECTED TRENCH CAPACITORS IN A CELL 失效
标题翻译：具有多个并联连接的电容器的多端口存储器
公开(公告)号：US20070189057A1
公开(公告)日：2007-08-16
申请号：US11306749
申请日：2006-01-10
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman , Carl Radens , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Mandelman , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： G11C8/16 , G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10861
摘要： An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors connected together as a unitary source of capacitance. A first access transistor is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.
摘要翻译：提供一种集成电路，其包括每个存储器单元具有多个端口的存储器，用于访问多个存储器单元中的每一个内的数据位。这种存储器包括存储单元的阵列，其中每个存储单元包括连接在一起作为整体电容源的多个电容器。第一存取晶体管耦合在多个电容器中的第一电容器和第一位线之间，第二存取晶体管耦合在多个电容器中的第二电容器和第二位线之间。在每个存储单元中，第一存取晶体管的栅极连接到第一字线，第二存取晶体管的栅极连接到第二字线。

76. 发明授权

US07247905B2 Offset vertical device 失效
标题翻译：偏移垂直装置
公开(公告)号：US07247905B2
公开(公告)日：2007-07-24
申请号：US10813352
申请日：2004-03-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10867 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： The present invention includes a method for forming a memory array and the memory array produced therefrom. Specifically, the memory array includes at least one first-type memory device, each of the at least one first-type memory device comprising a first transistor and a first underlying capacitor that are in electrical contact to each other through a first buried strap, where the first buried strap positioned on a first collar region; and at least one second-type memory cell, where each of the at least are second-type memory device comprises a second transistor and a second underlying capacitor that are in electrical contact through an offset buried strap, where the offset buried strap is positioned on a second collar region, wherein the second collar region has a length equal to the first collar region.
摘要翻译：本发明包括一种用于形成存储器阵列的方法和由其制成的存储器阵列。具体而言，存储器阵列包括至少一个第一型存储器件，至少一个第一型存储器件中的每一个包括通过第一掩埋带彼此电接触的第一晶体管和第一底层电容器，其中位于第一环区的第一掩埋带; 以及至少一个第二类型存储单元，其中至少第二类型存储器件中的每一个包括第二晶体管和第二底层电容器，所述第二晶体管和第二底层电容器通过偏移掩埋带电接触，其中所述偏移掩埋带位于第二衣领区域，其中第二衣领区域具有等于第一衣领区域的长度。

77. 发明申请

US20070047293A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 有权
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20070047293A1
公开(公告)日：2007-03-01
申请号：US11161962
申请日：2005-08-24
申请人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
发明人： Jack Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl Radens , Geng Wang
IPC分类号： G11C11/24
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

78. 发明申请

US20120205732A1 INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT 有权
标题翻译：集成电路，包含通过过度接触电路连接到TRENCH电容器的有源晶体管
公开(公告)号：US20120205732A1
公开(公告)日：2012-08-16
申请号：US13454635
申请日：2012-04-24
申请人： John E. Barth, JR. , Kangguo Cheng , Michael Sperling , Geng Wang
发明人： John E. Barth, JR. , Kangguo Cheng , Michael Sperling , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L21/76895 , H01L23/485 , H01L27/10867 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.
摘要翻译：集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器有源晶体管。

79. 发明授权

US07923815B2 DRAM having deep trench capacitors with lightly doped buried plates 有权
标题翻译： DRAM具有具有轻掺杂掩埋板的深沟槽电容器
公开(公告)号：US07923815B2
公开(公告)日：2011-04-12
申请号：US11969986
申请日：2008-01-07
申请人： Geng Wang , Kangguo Cheng , Johnathan E. Faltermeier , Paul C. Parries
发明人： Geng Wang , Kangguo Cheng , Johnathan E. Faltermeier , Paul C. Parries
IPC分类号： H01L21/02
CPC分类号： H01L29/66181 , G11C11/404 , H01L27/0805 , H01L27/10861
摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.
摘要翻译：通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。电容器可以是DRAM / eDRAM单元的存储电容器。掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍。

80. 发明授权

US07723201B2 Structure and method for making on-chip capacitors with various capacitances 有权
标题翻译：制造具有各种电容的片上电容器的结构和方法
公开(公告)号：US07723201B2
公开(公告)日：2010-05-25
申请号：US11306718
申请日：2006-01-09
申请人： Kangguo Cheng , Geng Wang
发明人： Kangguo Cheng , Geng Wang
IPC分类号： H01L21/20 , H01L29/04
CPC分类号： H01L29/66181 , H01L27/0207 , H01L27/0805 , H01L27/1087
摘要： A method for manufacturing a device includes forming trenches of different morphologies into a substrate. At the upper surfaces, the trenches have different orientations with respect to each other. In an aspect, windows for the trenches are aligned along the and directions of a silicon substrate. The trenches of different morphologies may be formed into capacitors having different capacitance levels. Also included are devices prepared by the method.
摘要翻译：一种制造器件的方法包括将不同形态的沟槽形成衬底。在上表面，沟槽具有相对于彼此的不同取向。在一个方面，用于沟槽的窗口沿着硅衬底的<100>和<110>方向排列。不同形态的沟槽可以形成为具有不同电容电平的电容器。还包括通过该方法制备的装置。

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