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71. 发明授权

US4872002A Integrated matrix display circuitry 失效
标题翻译：集成矩阵显示电路
公开(公告)号：US4872002A
公开(公告)日：1989-10-03
申请号：US150817
申请日：1988-02-01
申请人： Roger G. Stewart , Dora Plus
发明人： Roger G. Stewart , Dora Plus
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/3688 , G09G3/3648 , G09G3/3677 , G09G2310/0205 , G09G2310/0224 , G09G2310/0297
摘要： Integrated latch circuitry for driving row or column busses of a matrix device fabricated in low mobility semiconductor material includes cross coupled transistors having variable impedance load devices. The cross coupled transistors are coupled between relatively positive and relatively negative supply potentials. The relatively negative supply potential is modulated to preset the state of the latches in order to reduce the load on input circuitry applying data to the latch. The variable impedance loads are modulated between relatively high and relatively low impedances to enhance the speed at which the latches change state.
摘要翻译：用于驱动以低迁移率半导体材料制造的矩阵器件的行或列总线的集成锁存电路包括具有可变阻抗负载器件的交叉耦合晶体管。交叉耦合晶体管耦合在相对正的和相对负的电源之间。相对负的电源电位被调制以预设锁存器的状态，以便减少将数据应用到锁存器的输入电路上的负载。可变阻抗负载在相对较高和相对较低的阻抗之间进行调制，以提高锁存器改变状态的速度。

72. 发明授权

US4760557A Radiation hard memory cell circuit with high inverter impedance ratio 失效
标题翻译：具有高逆变器阻抗比的辐射硬存储单元电路
公开(公告)号：US4760557A
公开(公告)日：1988-07-26
申请号：US904156
申请日：1986-09-05
申请人： Roger G. Stewart , Dora Plus
发明人： Roger G. Stewart , Dora Plus
IPC分类号： G11C5/00 , G11C11/412 , H01L27/11 , G11C5/02 , G11C11/34 , G11C11/40
CPC分类号： H01L27/1104 , G11C11/4125 , G11C5/005
摘要： A memory cell circuit has a pair of cross-coupled inverters. One inverter has an output impedance at least 10 times, preferably, at least 50 times, that of the other inverter so that during a radiation pulse the chance of a change in logic state is reduced. In a particular embodiment, the one inverter has an output impedance of 135 times that of the other inverter.
摘要翻译：存储单元电路具有一对交叉耦合的反相器。一个逆变器的输出阻抗比其他逆变器的输出阻抗的至少10倍，优选地至少是50倍，使得在放射脉冲期间，逻辑状态改变的机会减小。在一个具体实施例中，一个逆变器的输出阻抗是另一个反相器的135倍。

73. 发明授权

US4742346A System for applying grey scale codes to the pixels of a display device 失效
标题翻译：将灰度代码应用于显示装置的像素的系统
公开(公告)号：US4742346A
公开(公告)日：1988-05-03
申请号：US943709
申请日：1986-12-19
申请人： Glynn G. Gillette , Roger G. Stewart , John T. Fischer
发明人： Glynn G. Gillette , Roger G. Stewart , John T. Fischer
IPC分类号： G09G3/20 , G09G3/36
CPC分类号： G09G3/2011 , G09G3/3688 , G09G2310/0259 , G09G2310/027 , G09G2310/0297
摘要： A system for applying grey scale codes to a display device having a plurality of columns of pixels, has a segmented shift register, with one shift register segment for each pixel column. Data stored in the shift register segments are transferred to counters through multiplex circuitry. The counters control transfer gates by which voltages are applied to the pixel columns.
摘要翻译：用于将灰度代码应用于具有多列像素的显示装置的系统具有分段移位寄存器，每个像素列具有一个移位寄存器段。存储在移位寄存器段中的数据通过复用电路传送到计数器。计数器控制传输门，电压被施加到像素列。

74. 发明授权

US4527081A Overshoot predriven semi-asynchronous driver 失效
标题翻译：超前预驱动的半异步驱动
公开(公告)号：US4527081A
公开(公告)日：1985-07-02
申请号：US465851
申请日：1983-02-11
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： H03K19/017 , H03K3/01 , H03K17/687
CPC分类号： H03K19/01707
摘要： An output driver circuit for fast memories and microprocessors and the li The driver circuit is responsive to a binary input voltage and includes first and second signal control paths respectively coupled to a pair of series connected output stage transistors coupled between two high and low reference voltages and switched alternately between conducting and non-conducting states in mutual opposition to provide a binary output voltage substantially equal to either of the two reference voltages depending upon the binary state of the input voltage. Additionally included is an anticipatory circuit having means responsive to both an externally applied precharge signal and a feedback signal corresponding to the binary state of the output voltage which alternately predrive the transistors close to their respective conducting switching points for increasing the speed of transition of the transistors between conductive and non-conductive states.
摘要翻译：用于快速存储器和微处理器等的输出驱动器电路。驱动器电路响应于二进制输入电压并且包括分别耦合到耦合在两个高参考电压和低参考电压之间的一对串联连接的输出级晶体管的第一和第二信号控制路径，并且相互反对地在导通状态和非导通状态之间交替切换以根据输入电压的二进制状态提供基本上等于两个参考电压中的任一个的二进制输出电压。另外包括预期电路，其具有响应于外部施加的预充电信号和对应于输出电压的二进制状态的反馈信号的装置，其交替地预先使晶体管接近其各自的导通开关点，以增加晶体管的转变速度在导电状态和非导通状态之间。

75. 发明授权

US4472805A Memory system with error storage 失效
标题翻译：存储系统存储错误
公开(公告)号：US4472805A
公开(公告)日：1984-09-18
申请号：US362464
申请日：1982-03-26
申请人： Ihor T. Wacyk , Andrew G. F. Dingwall , Roger G. Stewart
发明人： Ihor T. Wacyk , Andrew G. F. Dingwall , Roger G. Stewart
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1076
摘要： A memory system stores bits which are read-out internally a word at a time and from which one or more bits may be selected for external read-out. Each time a bit is written into the memory the parity of the word into which the bit is written is checked and a parity bit generated and stored for the word. The parity of the words originally read internally from the memory is checked and any parity errors detected are stored as error signals. Each time a word subsequently is read internally from the memory, if there is stored for that word an error signal, and if it is also determined that the bit selected from that word for external read-out is in error, that bit automatically is corrected even if the parity of the word is found to be correct.
摘要翻译：存储器系统一次存储在内部读出字的位，并且可以从其中选择一个或多个位用于外部读出。每次将一位写入存储器时，检查写入该位的字的奇偶校验，并生成并存储该字的奇偶校验位。检查原先从存储器内部读取的字的奇偶校验，并且检测到的任何奇偶校验错误被存储为错误信号。每次随后从存储器内部读取一个字，如果存在该字的错误信号，并且如果还确定从该字中选择用于外部读出的位是错误的，该位自动被校正即使发现这个词的奇偶校验是正确的。

76. 发明授权

US4419741A Read only memory (ROM) having high density memory array with on pitch decoder circuitry 失效
标题翻译：具有高密度存储器阵列的只读存储器（ROM）具有音调解码器电路
公开(公告)号：US4419741A
公开(公告)日：1983-12-06
申请号：US299343
申请日：1981-09-04
申请人： Roger G. Stewart , Moshe Mazin
发明人： Roger G. Stewart , Moshe Mazin
IPC分类号： G11C17/06 , H01L27/12 , G11C5/06
CPC分类号： H01L27/12 , G11C17/06
摘要： The ROM utilizes a diode x-y memory array which can be comprised of a number of suitable materials which form rectifying junctions. The diodes are formed vertically in order to provide a very high density array. On pitch decoder circuitry which is capable of matching the high density of the memory cells in the x-y memory array is also described, as is a unique apparatus for joining adjacent ends of conductive lines which are spaced very close together without increasing their pitch.
摘要翻译： ROM使用二极管x-y存储器阵列，其可以由形成整流结的许多合适的材料组成。二极管垂直形成，以提供非常高密度的阵列。还描述了能够匹配x-y存储器阵列中的高密度存储器单元的音调解码器电路，作为用于连接非常靠近在一起而不增加它们的音调的导线的相邻端的独特设备。

77. 发明授权

US4405996A Precharge with power conservation 失效
标题翻译：预充电省电
公开(公告)号：US4405996A
公开(公告)日：1983-09-20
申请号：US232303
申请日：1981-02-06
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G11C11/41 , G11C8/00 , G11C8/08 , G11C8/18 , G11C11/413 , H03K5/135 , H03K19/017 , G11C7/00
CPC分类号： G11C8/18 , G11C8/00 , G11C8/08 , H03K19/01742 , H03K5/135 , G11C2207/061
摘要： A circuit having a "selected" and a "deselected" operating mode includes a controllable latch which is operable when the circuit is "deselected" and a controllable pulse generating network which is operable when the circuit is "selected". The latch senses and stores a signal evidencing a change of state of any one of certain input signals to the circuit when the circuit is deselected. The pulse network is responsive to the stored signal and produces a pulse, indicative of the occurrence of a change, when the circuit is subsequently selected.
摘要翻译：具有“选择”和“取消选择”操作模式的电路包括可控制的锁存器，其在电路被“取消选择”时可操作，以及可控脉冲发生网络，其在电路被“选择”时可操作。当取消选择电路时，锁存器感测并存储证明某些输入信号中任一个的状态改变到电路的信号。当随后选择电路时，脉冲网络响应于存储的信号并产生指示变化的发生的脉冲。

78. 发明授权

US4386284A Pulse generating circuit using current source 失效
标题翻译：脉冲发生电路采用电流源
公开(公告)号：US4386284A
公开(公告)日：1983-05-31
申请号：US232360
申请日：1981-02-06
申请人： Ihor T. Wacyk , Roger G. Stewart
发明人： Ihor T. Wacyk , Roger G. Stewart
IPC分类号： G11C8/00 , H03K5/01 , H03K17/687 , H03K19/017
CPC分类号： G11C8/00
摘要： A controllable impedance means and a controllable, relatively constant, current source are connected in parallel between the output line of a circuit and a first point of operating potential. Means responsive to the voltage on the output line control the conductivity of the controllable inpedance means and of the controllable current source to generate an output pulse having relatively sharp leading and trailing edges.
摘要翻译：可控阻抗装置和可控的相对恒定的电流源并联连接在电路的输出线和第一操作电位之间。响应于输出线路上的电压的装置控制可控阻抗装置和可控电流源的电导率，以产生具有相对尖锐的前沿和后沿的输出脉冲。

79. 发明授权

US4344005A Power gated decoding 失效
标题翻译：电源门控解码
公开(公告)号：US4344005A
公开(公告)日：1982-08-10
申请号：US44363
申请日：1979-06-01
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G11C8/10 , H03K19/0185 , H03M7/00 , H03K19/177 , G11C7/00 , H03K19/094 , H03K19/21
CPC分类号： G11C8/10 , H03K19/01855 , H03M7/005
摘要： A decoder in which the decoding of N input variables to produce 2.sup.N unique outputs is carried out in steps, and in which some of the signals to be decoded also function to power part of the decoding circuitry. First, X of the N variables are decoded separately, as a group, to produce 2.sup.X unique outputs while the remaining N-X variables are also separately decoded, as a group, to produce 2.sup.(N-X) unique outputs, where N and X are positive integers and X is less than N. Then, the outputs of the two groups are logically combined by means of 2.sup.N decoding buffer gates to produce 2.sup.N unique outputs. Each one of the 2.sup.X unique outputs is applied to the signal input terminals of 2.sup.(N-X) different ones of the 2.sup.N buffer gates and each one of the 2.sup.(N-X) unique outputs is used to power 2.sup.X different ones of the 2.sup.N buffer gates to produce 2.sup.N unique outputs of the N input variables, at the outputs of the buffer gates.
摘要翻译：其中N个输入变量的解码以产生2N个独特输出的解码器被执行，并且其中一些待解码的信号也用于为解码电路的一部分供电。首先，将N个变量的X作为一组单独解码，以产生2X个唯一输出，而剩余的NX变量也被单独解码为一组，以产生2（NX）唯一输出，其中N和X是正整数并且X小于N.然后，两组的输出通过2N个解码缓冲器门进行逻辑组合，以产生2N个独特的输出。 2X唯一输出中的每一个被应用于2N（N N）个不同2N个缓冲器门的信号输入端，并且2个（NX）唯一输出中的每一个用于为2N个缓冲门中的2X个不同的2个在缓冲门的输出处产生N个输入变量的2N个唯一输出。

80. 发明授权

US4339809A Noise protection circuits 失效
标题翻译：噪声保护电路
公开(公告)号：US4339809A
公开(公告)日：1982-07-13
申请号：US188887
申请日：1980-09-19
申请人： Roger G. Stewart
发明人： Roger G. Stewart
IPC分类号： G06F11/00 , G11C5/00 , G11C11/40
CPC分类号： G11C5/005 , G06F11/00
摘要： An integrated circuit (IC) such as a memory array is connected via a normally closed switch to a power supply. The switch is opened to isolate the IC (memory array) from the power supply during the time intervals that the IC (memory array) is vulnerable to noise transients that may be present on the power supply lines.
摘要翻译：诸如存储器阵列的集成电路（IC）通过常闭开关连接到电源。在IC（存储器阵列）容易受到可能存在于电源线上的噪声瞬变的时间间隔期间，该开关被打开以将IC（存储器阵列）与电源隔离。

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