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71. 发明申请

US20050130341A1 Selective synthesis of semiconducting carbon nanotubes 失效
标题翻译：半导体碳纳米管的选择性合成
公开(公告)号：US20050130341A1
公开(公告)日：2005-06-16
申请号：US10732951
申请日：2003-12-11
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： B82B3/00 , C01B31/02 , C30B25/02 , C30B29/02 , C30B29/60 , H01L29/15 , H01L29/786 , H01L51/30 , H01L21/336
CPC分类号： H01L51/0512 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B2202/22 , C01B2202/34 , C30B25/02 , C30B29/02 , C30B29/605 , H01L51/0048 , Y10S977/854
摘要： Methods for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on multiple synthesis sites carried by a substrate and structures formed thereby. After an initial growth stage, synthesis sites bearing conducting carbon nanotubes are altered to discontinue synthesis at these specific synthesis sites and, thereby, halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration so that semiconducting carbon nanotubes may be lengthened to a greater length than the conducting carbon nanotubes.
摘要翻译：从由衬底承载的多个合成位点上合成的导电和半导体碳纳米管的随机集合以及由此形成的结构选择半导体碳纳米管的方法。在初始生长阶段之后，改变承载导电碳纳米管的合成位点，以在这些特定合成位点停止合成，从而停止导电碳纳米管的延长。具有半导体碳纳米管的合成位点不受改变的影响，使得半导体碳纳米管可以被延长到比导电碳纳米管更长的长度。

72. 发明申请

US20080116529A1 SHALLOW TRENCH ISOLATION STRUCTURE FOR SHIELDING TRAPPED CHARGE IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于半导体器件中的屏蔽带电充电的低温隔离结构
公开(公告)号：US20080116529A1
公开(公告)日：2008-05-22
申请号：US12022202
申请日：2008-01-30
申请人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Ethan Cannon , Shunhua Chang , Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L27/088
CPC分类号： H01L21/76224 , H01L29/7833
摘要： A semiconductor structure comprising a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.
摘要翻译：一种包括第一场效应晶体管（FET），第二FET和浅沟槽隔离（STI）结构的半导体结构。第一FET包括由硅衬底的一部分形成的沟道区，在沟道区上形成的栅极电介质和包括与栅极电介质直接物理接触的底表面的栅电极。沟道区的顶表面位于第一平面内，栅电极的底表面位于第二平面内。 STI结构包括导电STI填充结构。导电STI填充结构的顶表面在第一平面上方高于第一距离D 1，并且在第二平面上方高于第二平面的第二距离D 2 2 < D 1 。

73. 发明申请

US20080102566A1 MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：多层和晶体平面取向半导体基板
公开(公告)号：US20080102566A1
公开(公告)日：2008-05-01
申请号：US11969279
申请日：2008-01-04
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

74. 发明申请

US20080044954A1 METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY 有权
标题翻译：制备垂直碳纳米管场效应晶体管的方法在阵列和场效应晶体管中的布置及其形成的阵列
公开(公告)号：US20080044954A1
公开(公告)日：2008-02-21
申请号：US11926627
申请日：2007-10-29
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Peter Mitchell , Larry Nesbit
IPC分类号： H01L21/8234
CPC分类号： H01L51/057 , B82Y10/00 , G11C13/025 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/66409 , H01L29/772 , H01L51/0048 , Y10S977/734
摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.
摘要翻译：一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。多个器件结构可以被配置为存储器电路或逻辑电路。

75. 发明申请

US20080017932A1 SHALLOW TRENCH ISOLATION FORMATION 有权
标题翻译：浅层分离形成
公开(公告)号：US20080017932A1
公开(公告)日：2008-01-24
申请号：US11866471
申请日：2007-10-03
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L29/72 , H01L29/76
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/02282 , H01L21/3143 , H01L21/3147 , H01L21/316 , H01L21/76224 , H01L21/823878
摘要： A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.
摘要翻译：一种用于形成半导体结构的方法和结构。提供半导体衬底。在半导体衬底内形成沟槽。第一层电绝缘材料形成在沟槽内。去除第一层电绝缘材料的第一部分和第二部分。选择性地在第一层上生长第二层电绝缘材料，该第一层包括去除的第一部分和被去除的第二部分。

76. 发明申请

US20070241412A1 BORDERLESS CONTACT STRUCTURES 有权
标题翻译：无边界接触结构
公开(公告)号：US20070241412A1
公开(公告)日：2007-10-18
申请号：US11679873
申请日：2007-02-28
申请人： Toshiharu Furukawa , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , David Horak , Charles Koburger
IPC分类号： H01L27/085
CPC分类号： H01L21/28518 , H01L21/76895 , H01L21/76897 , H01L27/11 , H01L27/1104
摘要： An SRAM cell. The SRAM cell including: a first gate segment common to a first PFET and a first NFET, a second gate segment common to a second PFET and a second NFET; a first silicide layer contacting a first end of the first gate segment and a drain of the second PFET; a second silicide layer contacting a sidewall contact region of the second gate segment and a drain of the first PFET; a third silicide layer contacting a sidewall contact region of the first gate segment and a drain of the second NFET; a fourth silicide layer contacting a first end of the second gate segment, a drain of the first PFET and a drain of a fourth NFET; and a fifth silicide layer contacting a second end of the first gate segment and a drain of a third NFET.
摘要翻译：一个SRAM单元。该SRAM单元包括：第一PFET和第一NFET公共的第一栅极段，与第二PFET和第二NFET共用的第二栅极段; 接触第一栅极段的第一端和第二PFET的漏极的第一硅化物层; 接触第二栅极段的侧壁接触区域和第一PFET的漏极的第二硅化物层; 接触第一栅极段的侧壁接触区域和第二NFET的漏极的第三硅化物层; 接触第二栅极段的第一端的第四硅化物层，第一PFET的漏极和第四NFET的漏极; 以及接触第一栅极段的第二端和第三NFET的漏极的第五硅化物层。

77. 发明申请

US20070099416A1 Shrinking Contact Apertures Through LPD Oxide 失效
标题翻译：通过LPD氧化物收缩接触孔
公开(公告)号：US20070099416A1
公开(公告)日：2007-05-03
申请号：US11163786
申请日：2005-10-31
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Larry Nesbit
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger , Larry Nesbit
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.
摘要翻译：通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。缩小的硬掩模然后限定通过电介质的亚光刻孔。

78. 发明申请

US20070096263A1 Accessible chip stack and process of manufacturing thereof 有权
标题翻译：无障碍芯片堆栈及其制造工艺
公开(公告)号：US20070096263A1
公开(公告)日：2007-05-03
申请号：US11266456
申请日：2005-11-03
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L29/40 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596 , H01L2924/0002
摘要： A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.
摘要翻译：制造三维集成电路芯片或晶片组件的过程，更具体地说，在将芯片定向成堆叠之前，将其布置在晶片上的处理。还公开了三维集成电路的制造，其中芯片密度可以非常高并且在晶片仍然完整且通常为平面结构的情况下被处理。

79. 发明申请

US20070059891A1 Mandrel/trim alignment in SIT processing 有权
标题翻译： SIT处理中的心轴/微调对齐
公开(公告)号：US20070059891A1
公开(公告)日：2007-03-15
申请号：US11226726
申请日：2005-09-14
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Qiqing Ouyang
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Qiqing Ouyang
IPC分类号： H01L21/467
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L29/66795
摘要： Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.
摘要翻译：本文公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，其需要将修剪掩模对准亚光刻特征以形成具有离散片段的硬掩模图案。在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

80. 发明申请

US20070025138A1 NON-VOLATILE SWITCHING AND MEMORY DEVICES USING VERTICAL NANOTUBES 有权
标题翻译：非挥发性开关和使用垂直纳米管的存储器件
公开(公告)号：US20070025138A1
公开(公告)日：2007-02-01
申请号：US11161183
申请日：2005-07-26
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/16 , G11C2213/77 , Y10S977/742 , Y10S977/939 , Y10S977/943
摘要： Non-volatile and radiation-hard switching and memory devices using vertical nano-tubes and reversibly held in state by van der Waals' forces and methods of fabricating the devices. Means for sensing the state of the devices include measuring capacitance, and tunneling and field emission currents.
摘要翻译：使用垂直纳米管的非易失性和辐射硬的开关和存储器件，并通过范德华力力可逆地保持状态和制造器件的方法。用于感测装置状态的装置包括测量电容，以及隧穿和场发射电流。

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