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71. 发明申请

US20080207613A1 Selective Kinase Inhibitors 审中-公开
标题翻译：选择性激酶抑制剂
公开(公告)号：US20080207613A1
公开(公告)日：2008-08-28
申请号：US10585916
申请日：2005-01-12
申请人： Michelle Leanne Styles , Jun Zeng , Herbert Rudolf Treutlein , Andrew Frederick Wilks , Marcel Robert Kling , Christopher John Burns , Xianyong Bu
发明人： Michelle Leanne Styles , Jun Zeng , Herbert Rudolf Treutlein , Andrew Frederick Wilks , Marcel Robert Kling , Christopher John Burns , Xianyong Bu
IPC分类号： A61K31/5377 , C07D403/04 , C07D403/14 , C07D401/04 , C07D407/14 , C07D409/14 , C07D413/14 , A61P37/06 , C07D401/14 , C07D235/04 , A61K31/497 , A61K31/4439 , A61K31/506 , A61K31/4184
CPC分类号： C07D403/04 , C07D235/30 , C07D241/20 , C07D401/12 , C07D401/14 , C07D405/12
摘要： A compound of the general formula (I) or pharmaceutically acceptable prodrugs, salts, hydrates, solvates, crystal forms or diastereomers thereof, wherein A represents a variety of six membered nitrogen containing heterocyclic rings, Q is a bond, halogen, C1-4 alkyl, O, S, SO2, CO or CS and X1, X2, X3 and X4 are optionally substituted by 9 specific substituents or one can be nitrogen. Compositions comprising a carrier and at least one compound of formula (I) are also provided. Further provided are methods of treating tyrosine kinase-associated disease states by administering a compound of formula (I) and methods of suppressing the immune system of a subject by administering a compound of formula (I).
摘要翻译：通式（I）的化合物或其药学上可接受的前药，盐，水合物，溶剂合物，结晶形式或非对映异构体，其中A表示多种六元含氮杂环，Q为键，卤素， 1-4烷基，O，S，SO 2，CO或CS和X 1，X 2，X _{3和X 4任选被9个特定取代基取代，或者可以是氮。还提供了包含载体和至少一种式（I）化合物的组合物。还提供了通过施用式（I）化合物和通过施用式（I）化合物来抑制受试者的免疫系统的方法来治疗酪氨酸激酶相关疾病状态的方法。}

72. 发明申请

US20080142909A1 ULTRA DENSE TRENCH-GATED POWER DEVICE WITH REDUCED DRAIN SOURCE FEEDBACK CAPACITANCE AND MILLER CHARGE 审中-公开
标题翻译：具有减少排水源反馈电容和铣床充电的超级密封式电镀式电源装置
公开(公告)号：US20080142909A1
公开(公告)日：2008-06-19
申请号：US11930673
申请日：2007-10-31
申请人： Jun Zeng
发明人： Jun Zeng
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/66734 , H01L29/7397 , H01L29/749
摘要： The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.
摘要翻译：功率器件的蜂窝结构包括具有高掺杂漏极区的衬底。在衬底上有相同掺杂的更轻掺杂的外延层。外延层上方是由相反型掺杂形成的阱区。覆盖阱是重掺杂的第一导电类型的上源层。沟槽结构包括侧壁氧化物或覆盖沟槽侧壁的其它合适的绝缘材料。沟槽的底部填充有掺杂多晶硅屏蔽层。诸如氮化硅的层间电介质覆盖屏蔽。栅极区域由另一层掺杂多晶硅形成。第二层间电介质（通常为硼磷硅玻璃（BPSG））覆盖栅极。在工作中，当适当的电压施加到栅极时，电流通过阱中的沟道在源极和漏极之间垂直流动。

73. 发明申请

US20070040214A1 Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and Miller charge 审中-公开
标题翻译：超密集沟槽门控功率器件具有减少的漏源反馈电容和Miller充电
公开(公告)号：US20070040214A1
公开(公告)日：2007-02-22
申请号：US11502594
申请日：2006-08-10
申请人： Jun Zeng
发明人： Jun Zeng
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/66734 , H01L29/7397 , H01L29/749
摘要： The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.
摘要翻译：功率器件的蜂窝结构包括具有高掺杂漏极区的衬底。在衬底上有相同掺杂的更轻掺杂的外延层。外延层上方是由相反型掺杂形成的阱区。覆盖阱是重掺杂的第一导电类型的上源层。沟槽结构包括侧壁氧化物或覆盖沟槽侧壁的其它合适的绝缘材料。沟槽的底部填充有掺杂多晶硅屏蔽层。诸如氮化硅的层间电介质覆盖屏蔽。栅极区域由另一层掺杂多晶硅形成。第二层间电介质（通常为硼磷硅玻璃（BPSG））覆盖栅极。在工作中，当适当的电压施加到栅极时，电流通过阱中的沟道在源极和漏极之间垂直流动。

74. 发明申请

US20060270132A1 Manufacturing process and structure of power junction field effect transistor 审中-公开
公开(公告)号：US20060270132A1
公开(公告)日：2006-11-30
申请号：US11194847
申请日：2005-08-01
申请人： Jun Zeng , Po-I Sun
发明人： Jun Zeng , Po-I Sun
IPC分类号： H01L21/337
CPC分类号： H01L29/8083 , H01L29/1066
摘要： A manufacturing process and a power junction field-effect transistor (JFET) are provided. The basic concept of the present invention is to allow the current to flow vertically from the drain region on the bottom side to the source region on the topside of the device. By regulating the voltage applied between the gate regions and the source region, the power junction field-effect transistor (JFET) of the present invention can be built to handle large current and higher voltage for power management purposes, as is similar to the metal oxide semiconductor field effect transistor (MOSFET).

75. 发明申请

US20060237782A1 Power semiconductor device with L-shaped source region 审中-公开
标题翻译：功率半导体器件具有L形源极区域
公开(公告)号：US20060237782A1
公开(公告)日：2006-10-26
申请号：US11194353
申请日：2005-08-01
申请人： Jun Zeng , Po-I Sun
发明人： Jun Zeng , Po-I Sun
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0869 , H01L29/1095
摘要： A power semiconductor device includes a substrate, a well region, a body region, a trench gate, a gate oxide layer, an L-shaped source region, an inter-layer dielectric layer and a metal layer. The body region is formed on the well region. The trench gate is formed at bilateral sides of the well region. The gate oxide layer is formed on sidewall and bottom of the trench gate. The L-shaped source region has a horizontal portion and a vertical portion formed on a portion of top region and bilateral sides of the body region, respectively. The inter-layer dielectric layer is formed on the trench gate and a portion of the L-shaped source region, thereby defining a contact window therein. The metal layer is formed on the inter-layer dielectric layer, the body region and the L-shaped source region, and connected to the L-shaped source region via the contact window.
摘要翻译：功率半导体器件包括衬底，阱区，体区，沟槽栅，栅极氧化层，L形源极区，层间电介质层和金属层。身体区域形成在井区域上。沟槽门形成在井区的双侧。栅极氧化层形成在沟槽栅极的侧壁和底部。 L形源区域具有分别形成在身体区域的顶部区域和双侧的一部分上的水平部分和垂直部分。层间电介质层形成在沟槽栅极和L形源极区域的一部分上，由此在其中限定接触窗口。金属层形成在层间电介质层，主体区域和L形源极区域上，并且经由接触窗口连接到L形源极区域。

76. 发明授权

US07098108B1 Semiconductor device having reduced effective substrate resistivity and associated methods 有权
公开(公告)号：US07098108B1
公开(公告)日：2006-08-29
申请号：US09551187
申请日：2000-04-17
申请人： Jun Zeng
发明人： Jun Zeng
IPC分类号： H01L21/336
CPC分类号： H01L29/7802 , H01L23/4827 , H01L24/32 , H01L29/0657 , H01L29/0834 , H01L29/417 , H01L29/41741 , H01L29/456 , H01L29/66333 , H01L2224/04026 , H01L2224/29101 , H01L2924/01004 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/10155 , H01L2924/10158 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： A semiconductor device includes at least one device active region formed in a first surface of a semiconductor substrate, an electrical contact layer on a second surface of the semiconductor substrate, and at least one resistivity-lowering body positioned in a corresponding recess in the substrate and connected to the electrical contact layer. The body preferably comprises a material having an electrical resistivity lower than an electrical resistivity of the semiconductor substrate to thereby lower an effective electrical resistivity of the substrate. The device active region may be an active region of a power control device, such as a MOSFET or IGBT, for example. The body may preferably comprise an electrical conductor such as copper, aluminum, silver, solder, or doped polysilicon. The at least one recess and associated resistivity-lowering body preferably defines a proportion of the semiconductor substrate area adjacent the device active region greater than about 0.4 percent, and may extend into the semiconductor substrate a distance greater than about 25 percent of a thickness of the substrate.

77. 发明授权

US06946348B2 Low voltage high density trench-gated power device with uniformity doped channel and its edge termination technique 有权
标题翻译：具有均匀掺杂通道的低压高密度沟槽门控功率器件及其边沿终止技术
公开(公告)号：US06946348B2
公开(公告)日：2005-09-20
申请号：US10795723
申请日：2004-03-05
申请人： Jun Zeng
发明人： Jun Zeng
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/78
CPC分类号： H01L29/7811 , H01L29/0657 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1095 , H01L29/407 , H01L29/66734 , H01L29/7813
摘要： Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.
摘要翻译：通过沟槽底部的掺杂剂注入将低功率沟槽MOSFET器件中的漂移区域合并在一起可以使用非常小的单元间距，导致非常高的沟道密度和均匀掺杂的沟道，从而显着降低渠道阻力。通过适当选择植入剂量和漂移区域的退火参数，可以严密控制器件的沟道长度，并且可以使沟道掺杂高度均匀。与常规器件相比，阈值电压降低，沟道电阻降低，并且漂移区导通电阻也降低。实现合并的漂移区域需要并入新的边缘终端设计，使得由P外延层和N + +衬底形成的PN结可以在晶片的边缘端接。

78. 发明授权

US06683346B2 Ultra dense trench-gated power-device with the reduced drain-source feedback capacitance and Miller charge 有权
标题翻译：超密集的沟槽门控功率器件，漏极 - 源极反馈电容减少和米勒充电
公开(公告)号：US06683346B2
公开(公告)日：2004-01-27
申请号：US10092692
申请日：2002-03-07
申请人： Jun Zeng
发明人： Jun Zeng
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/66734 , H01L29/7397 , H01L29/749
摘要： The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.
摘要翻译：功率器件的蜂窝结构包括具有高掺杂漏极区的衬底。在衬底上有相同掺杂的更轻掺杂的外延层。外延层上方是由相反型掺杂形成的阱区。覆盖阱是重掺杂的第一导电类型的上源层。沟槽结构包括侧壁氧化物或覆盖沟槽侧壁的其它合适的绝缘材料。沟槽的底部填充有掺杂多晶硅屏蔽层。诸如氮化硅的层间电介质覆盖屏蔽。栅极区域由另一层掺杂多晶硅形成。第二层间电介质（通常为硼磷硅玻璃（BPSG））覆盖栅极。在工作中，当适当的电压施加到栅极时，电流通过阱中的沟道在源极和漏极之间垂直流动。

79. 发明授权

US06445035B1 Power MOS device with buried gate and groove 有权
标题翻译：功率MOS器件具有掩埋栅极和沟槽
公开(公告)号：US06445035B1
公开(公告)日：2002-09-03
申请号：US09624533
申请日：2000-07-24
申请人： Jun Zeng , Gary M. Dolny , Christopher B. Kocon , Linda S. Brush
发明人： Jun Zeng , Gary M. Dolny , Christopher B. Kocon , Linda S. Brush
IPC分类号： H01L2994
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66363 , H01L29/7397 , H01L29/7455 , H01L29/7813
摘要： An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches. A groove in each of the highly doped source regions extends through the source regions into the well region and terminates in a nadir. A highly doped body region of a first conductance type is disposed in the well region adjacent both to the nadir of one or more of the grooves and to adjacent source regions penetrated by the grooves. A conductive layer is disposed over the substrate and electrically contacts the body and source regions. A process for fabricating a device produces an MOS power device that avoids the loss of channel width and provides reduced channel resistance without sacrificing device ruggedness and dynamic characteristics.
摘要翻译： MOS功率器件的衬底包括具有上表面和下面的漏极区的上层，设置在漏极区上的上层中的第一导电类型的阱区，以及多个间隔开的掩埋栅，包括从上层的上表面穿过阱区延伸到漏区的沟槽。每个沟槽包括衬在其表面上的绝缘材料，将其下部填充到基本上在上层的上表面下方的选定水平的导电材料，以及基本上填充沟槽其余部分的绝缘材料。第二导电类型的多个高掺杂源区被设置在邻近每个沟槽的上部的上层中，每个源区从上表面延伸到上层中的深度，以提供源区和沟槽中的导电材料。每个高掺杂源区域中的沟槽延伸穿过源区域进入阱区域并终止于最低点。第一导电类型的高掺杂体区域设置在与一个或多个凹槽的最低点相邻的阱区域中以及与沟槽穿透的相邻源极区域相邻的阱区域中。导电层设置在衬底上并与主体区域和源区域电接触。制造器件的工艺产生了MOS功率器件，其避免了沟道宽度的损失，并且在不牺牲器件耐用性和动态特性的情况下提供降低的沟道电阻。

80. 发明授权

US06351009B1 MOS-gated device having a buried gate and process for forming same 有权
标题翻译：具有掩埋栅极的MOS门控器件及其形成工艺
公开(公告)号：US06351009B1
公开(公告)日：2002-02-26
申请号：US09260411
申请日：1999-03-01
申请人： Christopher B. Kocon , Jun Zeng
发明人： Christopher B. Kocon , Jun Zeng
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/4236 , H01L29/66348 , H01L29/66734 , H01L29/7397
摘要： An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.
摘要翻译：改进的沟槽MOS门控器件包括单晶半导体衬底，其上配置有掺杂的上层。上层在上表面包括具有第一极性的多个重掺杂体区域，并且覆盖在漏极区域上。上层还在其上表面包括多个重掺杂的源极区域，其具有与主体区域A相反的第二极性。栅极沟槽从上层的上表面延伸到漏极区域，并且将一个源极区域与另一个源区域分离。沟槽具有包括介电材料层的底板和侧壁，并且包含填充到选定电平的导电栅极材料和覆盖栅极材料并基本上填充沟槽的介电材料隔离层。因此，沟槽中的上层电介质材料的上表面与上层的上表面基本上共面。用于形成改进的MOS栅极器件的工艺提供了一种器件，其栅极沟槽用导电栅极材料填充到选定的电平，在其上形成隔离电介质层，其上表面与上层的上表面基本共面的设备。

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