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    • 71. 发明授权
    • Optical test structure for measuring charge-transfer efficiency
    • 用于测量电荷转移效率的光学测试结构
    • US06803960B2
    • 2004-10-12
    • US09736936
    • 2000-12-14
    • John P. ShepherdEric G. Stevens
    • John P. ShepherdEric G. Stevens
    • H04N5335
    • H01L27/14818H01L27/1485
    • An optically operated test structure for testing the charge transfer efficiency (CTE) of a charge coupled device (CCD) solid-state image sensor. A solid-state image sensor includes a substrate of a semiconductor material of one conductivity type having a surface. A plurality of spaced, parallel CCDs are in the substrate at the surface. Each CCD includes a channel region and a plurality of conductive gates extending across and insulated from the channel region. The conductive gates extend laterally across the channel regions of all of the CCDs and divide the channel regions into a plurality of phases and pixels. A drain region of the opposite conductivity type is in the substrate at the surface and extends along the channel region of at least one of the CCDs. A simply connected (rectangular) region of the plurality of spaced, parallel CCDs is photoactive. The CCDs outside this photoactive region are typically covered with metal or some other optically opaque material. One or more of the parallel CCD columns comprise optical test structures at the start and end of the CCD array and are photoactive. One or more parallel regions are adjacent and abutting on either side of the test structures; these may or may not be photoactive. These surrounding, adjacent regions are connected to a drain on the imager; the drain collects any charge captured in these adjacent regions. Each of the plurality of spaced, parallel, vertical CCDs is connected to one or more horizontal CCDs oriented in a direction perpendicular to the vertical CCDs.
    • 一种用于测试电荷耦合器件(CCD)固态图像传感器的电荷转移效率(CTE)的光学测试结构。 固态图像传感器包括具有表面的一种导电类型的半导体材料的衬底。 多个间隔开的平行CCD位于表面的基板中。 每个CCD包括沟道区域和延伸跨过沟道区域并且与沟道区域绝缘的多个导电栅极。 导电栅极跨越所有CCD的沟道区域横向延伸,并将沟道区域分成多个相位和像素。 相反导电类型的漏区在表面处于衬底中并且沿着至少一个CCD的沟道区延伸。 多个间隔开的并联CCD的简单连接(矩形)区域是光活性的。 该光活性区域外的CCD通常被金属或其它不透光材料覆盖。 并行CCD列中的一个或多个包括在CCD阵列的开始和结束处的光学测试结构,并且是光活性的。 一个或多个平行区域在测试结构的两侧相邻并邻接; 这些可能或可能不是光敏的。 这些周围的相邻区域连接到成像器上的漏极; 漏极收集在这些相邻区域捕获的任何电荷。 多个相互平行的垂直CCD中的每一个连接到垂直于垂直CCD的方向上定向的一个或多个水平CCD。
    • 74. 发明授权
    • Self aligned LOD antiblooming structure for solid-state imagers
    • 固态成像器的自对准LOD防护结构
    • US6051852A
    • 2000-04-18
    • US891290
    • 1997-07-10
    • Eric G. Stevens
    • Eric G. Stevens
    • H01L27/148H01L29/768
    • H01L27/14887
    • A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.
    • 自对准的横向溢流漏极防护结构对漏极偏置电压不敏感,因此对工艺变化的不敏感性提高。 通过光刻可以容易地调节和确定防起泡屏障区域的长度。 自对准的横向溢流排水(LOD)防爆结构导致节省空间的设计,从而提高整体传感器性能。 在这种结构中,提供了比将像素彼此分开的屏障更小(伏特)的抗电势势垒,使得与相邻像素相反,过量电荷优先流入LOD。
    • 75. 发明授权
    • Method of making two-phase buried channel planar gate CCD
    • 制造两相埋管平面栅极CCD的方法
    • US5298448A
    • 1994-03-29
    • US995393
    • 1992-12-18
    • Eric G. StevensStephen L. Kosman
    • Eric G. StevensStephen L. Kosman
    • H01L29/762H01L21/339H01L29/768
    • H01L29/66954H01L29/76841Y10S438/947
    • The present invention is directed to a method of making a true two-phase CCD using a single layer (level) of the conductive material for the gate electrodes to provide a planar structure. The method includes using L-shaped masking layers having a submicron length of a bottom portion between two masking layers of silicon dioxide on and spaced along a surface of a conductive layer. The conductive layer is over and insulated from a surface of a body of a semiconductor material having a channel region therein. The L-shaped masking layers are removed to expose a spaced narrow portions of the conductive layer. The conductive layer is then etched completely therethrough at each exposed portion to divide the conductive layer into gate electrodes which are spaced apart by submicron width gaps.
    • 本发明涉及一种使用用于栅电极的导电材料的单层(层)制造真正的两相CCD以提供平面结构的方法。 该方法包括在导电层的表面上并沿间隔开的二氧化硅屏蔽层之间使用具有底部的亚微米长度的L形掩模层。 导电层与其中具有沟道区的半导体材料的主体的表面结合并绝缘。 去除L形掩模层以露出导电层的间隔的狭窄部分。 然后,在每个暴露部分,完全蚀刻导电层,以将导电层划分成由亚微米宽度间隔间隔开的栅电极。