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71. 发明授权

US08310866B2 MRAM device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations 有权
标题翻译：采用热辅助写入操作和热辅助自参考操作的MRAM器件结构
公开(公告)号：US08310866B2
公开(公告)日：2012-11-13
申请号：US12168671
申请日：2008-07-07
申请人： Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
发明人： Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
IPC分类号： G11C11/02 , G11C7/00 , H01L21/00
CPC分类号： G11C7/04 , B82Y25/00 , B82Y40/00 , G11C11/16 , G11C11/1675 , H01F10/3254 , H01F10/3272 , H01F41/307 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.
摘要翻译：提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。阻挡层被定位在第二磁性层和自由磁性层之间。

72. 发明授权

US07903454B2 Integrated circuit, memory cell array, memory module, and method of operating an integrated circuit 有权
标题翻译：集成电路，存储单元阵列，存储器模块和操作集成电路的方法
公开(公告)号：US07903454B2
公开(公告)日：2011-03-08
申请号：US12114466
申请日：2008-05-02
申请人： Dietmar Gogl , Rainer Leuschner , Ulrich Klostermann
发明人： Dietmar Gogl , Rainer Leuschner , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.
摘要翻译：根据本发明的一个实施例，集成电路包括多个热可选择存储单元，每个存储单元连接到导电线，该导线具有用于施加加热电流的第一部分和用于施加加热电流的第二部分编程电流。集成电路被配置为使得加热电流和编程电流可以彼此独立地分别路由到导线的第一和第二部分。

73. 发明授权

US07903452B2 Magnetoresistive memory cell 有权
标题翻译：磁阻记忆体
公开(公告)号：US07903452B2
公开(公告)日：2011-03-08
申请号：US11473531
申请日：2006-06-23
申请人： Rok Dittrich , Ulrich Klostermann
发明人： Rok Dittrich , Ulrich Klostermann
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/5607
摘要： A magnetoresistive memory cell has a magnetic stack providing an effective anisotropy field of a storage layer of the magnetic stack during thermal select heating, at least one line providing at least one external magnetic field to the magnetic stack, the effective anisotropy field and the at least one external magnetic field having a non-zero angle relative to one another.
摘要翻译：磁阻存储单元具有磁堆栈，其在热选择加热期间提供磁堆栈的存储层的有效各向异性场，至少一行向磁堆提供至少一个外部磁场，有效各向异性场和至少一个外部磁场相对于彼此具有非零角度。

74. 发明授权

US07838861B2 Integrated circuits; methods for manufacturing an integrated circuit and memory module 有权
标题翻译：集成电路; 用于制造集成电路和存储器模块的方法
公开(公告)号：US07838861B2
公开(公告)日：2010-11-23
申请号：US11856668
申请日：2007-09-17
申请人： Ulrich Klostermann
发明人： Ulrich Klostermann
IPC分类号： H01L29/02
CPC分类号： H01L27/2463 , H01L45/085 , H01L45/1226 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1658
摘要： Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate having a main processing surface, at least two first electrodes, wherein each of the two first electrodes has a side surface being arranged at a respective angle with regard to the main processing surface, the side surfaces facing one another. The programmable arrangement may further include at least one second electrode and ion conducting material between each of the at least two first electrodes and the at least one second electrode, wherein the at least one second electrode is arranged partially between the side surfaces of the two first electrodes facing one another.
摘要翻译：本发明的实施例一般涉及集成电路，制造集成电路和存储器模块的方法。在本发明的实施例中，提供具有可编程布置的集成电路。可编程布置包括具有主处理表面的基板，至少两个第一电极，其中两个第一电极中的每一个具有相对于主处理表面相对于主处理表面相对的角度布置的侧表面。所述可编程布置还可以包括在所述至少两个第一电极和所述至少一个第二电极中的每一个之间的至少一个第二电极和离子传导材料，其中所述至少一个第二电极部分地布置在所述两个第一电极电极彼此面对。

75. 发明授权

US07751231B2 Method and integrated circuit for determining the state of a resistivity changing memory cell 失效
标题翻译：用于确定电阻率变化的存储单元的状态的方法和集成电路
公开(公告)号：US07751231B2
公开(公告)日：2010-07-06
申请号：US12115433
申请日：2008-05-05
申请人： Peter Schrogmeier , Ulrich Klostermann
发明人： Peter Schrogmeier , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5607
摘要： A method and an integrated circuit for determining the state of a resistivity changing memory cell. In one embodiment the method includes detecting a first resistance of the resistivity changing memory cell, determining whether the first resistance value is smaller than a predetermined threshold value thereby determining a first result value, initializing the resistivity changing memory cell into one of at least four resistivity changing memory states, detecting a second resistance value of the resistivity changing memory cell, determining whether the second resistance value is smaller than the predetermined threshold value determining a second result value, and determining the state of the resistivity changing memory cell state using the first and the second result values.
摘要翻译：一种用于确定电阻率变化存储单元的状态的方法和集成电路。在一个实施例中，该方法包括检测电阻率变化存储单元的第一电阻，确定第一电阻值是否小于预定阈值，由此确定第一结果值，将电阻率变化存储单元初始化为至少四个电阻率改变存储器状态，检测电阻率变化存储单元的第二电阻值，确定第二电阻值是否小于确定第二结果值的预定阈值，以及使用第一和第二电阻值确定电阻率变化存储单元状态的状态，第二个结果值。

76. 发明授权

US07715225B2 Memory cell using spin induced switching effects 失效
标题翻译：存储单元使用自旋感应开关效应
公开(公告)号：US07715225B2
公开(公告)日：2010-05-11
申请号：US12036518
申请日：2008-02-25
申请人： Wolfgang Raberg , Ulrich Klostermann
发明人： Wolfgang Raberg , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： H01L27/222 , G11C11/1673 , G11C11/1675 , H01L43/08
摘要： According to an embodiment, an integrated circuit includes a magneto-resistive memory cell. The magneto-resistive memory cell includes: a first ferromagnetic layer; a second ferromagnetic layer; and a nonmagnetic layer being disposed between the first ferromagnetic layer and the second ferromagnetic layer. The integrated circuit further includes a programming circuit configured to route a programming current through the magneto-resistive memory cell, wherein the programming current programs the magnetizations of the first ferromagnetic layer and of the second ferromagnetic layer by spin induced switching effects.
摘要翻译：根据实施例，集成电路包括磁阻存储单元。磁阻存储单元包括：第一铁磁层; 第二铁磁层; 并且非磁性层设置在第一铁磁层和第二铁磁层之间。集成电路还包括编程电路，其被配置为将编程电流路由到磁阻存储器单元，其中编程电流通过自旋感应开关效应对第一铁磁层和第二铁磁层的磁化进行编程。

77. 发明申请

US20100013035A1 Integrated Circuit, Memory Module, and Method of Manufacturing an Integrated Circuit 有权
标题翻译：集成电路，存储器模块和制造集成电路的方法
公开(公告)号：US20100013035A1
公开(公告)日：2010-01-21
申请号：US12175236
申请日：2008-07-17
申请人： Manfred Ruehrig , Ulrich Klostermann , Michael Vieth
发明人： Manfred Ruehrig , Ulrich Klostermann , Michael Vieth
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： H01L27/222 , G11C11/161 , G11C11/1659
摘要： An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer.
摘要翻译：集成电路包括多个磁隧道结叠层，每个磁隧道结堆叠包括参考层，阻挡层和自由层，其中多个磁隧道结堆叠共享连续的公共参考层。

78. 发明申请

US20090073749A1 INTEGRATED CIRCUIT, CELL ARRANGEMENT, METHOD OF OPERATING AN INTEGRATED CIRCUIT, MEMORY MODULE 失效
标题翻译：集成电路，电池布置，运算集成电路的方法，存储器模块
公开(公告)号：US20090073749A1
公开(公告)日：2009-03-19
申请号：US11856656
申请日：2007-09-17
申请人： Rok Dittrich , Ulrich Klostermann
发明人： Rok Dittrich , Ulrich Klostermann
IPC分类号： G11C11/10
CPC分类号： H01L27/228 , G11C11/1675 , G11C11/1693
摘要： An integrated circuit having a cell arrangement is provided. The cell arrangement includes at least one magnetoresistive memory cell, a first line providing a first line current, and a second line providing a second line current. The cell arrangement further includes a controller controlling the application of the first line current and the second line current, such that while the first line current is active, a transition of a magnetic field provided by a change of the second line current is provided such that the transition time of the magnetic field is shorter than the time required for the magnetization of the magnetoresistive memory cell to relax into a changed equilibrium state.
摘要翻译：提供具有单元布置的集成电路。单元布置包括至少一个磁阻存储单元，提供第一线电流的第一线和提供第二线电流的第二线。电池装置还包括控制第一线路电流和第二线路电流的应用的控制器，使得当第一线路电流有效时，提供由第二线路电流的变化提供的磁场的转变，使得磁场的转变时间比磁阻存储单元的磁化松弛进入变化的平衡状态所需的时间短。

79. 发明申请

US20080094881A1 Hybrid Memory Cell for Spin-Polarized Electron Current Induced Switching and Writing/Reading Process Using Such Memory Cell 有权
标题翻译：用于旋转极化电子电流的混合存储单元使用这种存储单元的切换和写入/读取过程
公开(公告)号：US20080094881A1
公开(公告)日：2008-04-24
申请号：US11845525
申请日：2007-08-27
申请人： Jacques Miltat , Yoshinobu Nakatani , Ulrich Klostermann
发明人： Jacques Miltat , Yoshinobu Nakatani , Ulrich Klostermann
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive hybrid memory cell includes first and second stacked structures. The first stacked structure includes a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein the first magnetic region has a fixed first magnetic moment vector and the second magnetic region has a free second magnetic moment vector that is switchable between the same and opposite directions with respect to the fixed first magnetic moment vector. The second stacked structure is at least partly arranged in a lateral relationship with respect to the first stacked structure and includes a third magnetic region having a fixed third magnetic moment vector and the second magnetic region. The first and second structures are arranged between at least two electrodes in electrical contact therewith.
摘要翻译：磁阻混合存储单元包括第一和第二堆叠结构。第一堆叠结构包括磁隧道结，该磁隧道结包括由非磁性材料层隔开的并联叠置的堆叠的第一和第二磁区，其中第一磁区具有固定的第一磁矩矢量，第二磁区具有相对于固定的第一磁矩矢量可在相同和相反方向之间切换的自由的第二磁矩矢量。第二堆叠结构至少部分地相对于第一堆叠结构布置在横向关系中，并且包括具有固定的第三磁矩矢量和第二磁性区域的第三磁性区域。第一和第二结构布置在与其接触的至少两个电极之间。

80. 发明申请

US20070296007A1 Shared ground contact isolation structure for high-density magneto-resistive RAM 审中-公开
标题翻译：用于高密度磁阻RAM的共享接地隔离结构
公开(公告)号：US20070296007A1
公开(公告)日：2007-12-27
申请号：US11369195
申请日：2006-03-06
申请人： Human Park , Ulrich Klostermann
发明人： Human Park , Ulrich Klostermann
IPC分类号： H01L29/772 , G11C11/00
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228
摘要： A buried ground contact that connects the ground electrodes of transistors in adjacent memory cells that are separated by an isolation region is described. In some embodiments, the buried ground contact passes beneath the isolation region that separates cells to electrically connect the drain regions of transistors in adjacent cells. The buried ground may be connected to a metal ground line through via connections at intervals, outside of the active cell area. Use of this buried ground contact eliminates the need for individual ground connections to each cell, leading to a substantial reduction in cell size, and a consequent increase in cell density. The buried ground contacts of the invention can be used with a variety of devices, including MRAM and PCRAM devices.
摘要翻译：描述了连接由隔离区分隔开的相邻存储单元中的晶体管的接地电极的埋地接地触点。在一些实施例中，埋地接触通过隔离单元的隔离区下方，以电连接相邻单元中的晶体管的漏极区。埋地可以在活动单元区域之外的间隔通过连接连接到金属接地线。使用这种埋地接触消除了对每个电池的单独接地连接的需要，导致电池尺寸的显着降低，并且随之而来的电池密度增加。本发明的埋地触点可以与各种装置一起使用，包括MRAM和PCRAM装置。

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