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71. 发明授权

US09594859B1 Apparatus and associated methods for parallelizing clustering and placement 有权
标题翻译：用于并行聚类和放置的装置和相关方法
公开(公告)号：US09594859B1
公开(公告)日：2017-03-14
申请号：US12040730
申请日：2008-02-29
申请人： Ketan Padalia , Adrian Ludwin , Ryan Fung , Vaughn Betz
发明人： Ketan Padalia , Adrian Ludwin , Ryan Fung , Vaughn Betz
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F9/46 , G06F17/10 , G06F17/504 , G06F17/505 , G06F17/5054 , G06F17/5072
摘要： A system for parallelizing software in computer-aided design (CAD) software for circuit design includes a computer. The computer is configured to form or optimize a plurality of clusters in parallel. Each cluster in the plurality of clusters includes a set of nodes in a netlist in a design. The computer is configured to determine placements for blocks in a netlist in parallel, based on iterative improvement, partitioning, or analytic techniques.
摘要翻译：用于电路设计的计算机辅助设计（CAD）软件中并行化软件的系统包括计算机。计算机被配置为并行地形成或优化多个簇。多个群集中的每个群集包括设计中网表中的一组节点。计算机被配置为基于迭代改进，分区或分析技术来并行地确定网表中的块的布局。

72. 发明授权

US08572530B1 Method and apparatus for performing path-level skew optimization and analysis for a logic design 有权
标题翻译：用于执行逻辑设计的路径级偏移优化和分析的方法和装置
公开(公告)号：US08572530B1
公开(公告)日：2013-10-29
申请号：US12928245
申请日：2010-12-06
申请人： Ryan Fung , Vaughn Betz , David Karchmer
发明人： Ryan Fung , Vaughn Betz , David Karchmer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F1/10
摘要： A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.
摘要翻译：一种用于设计系统的方法，包括优化系统中的路径级偏差并分析系统中的路径级偏差。还公开了其他实施例。

73. 发明授权

US08296709B2 Method and apparatus for performing parallel routing using a multi-threaded routing procedure 有权
标题翻译：使用多线程路由过程执行并行路由的方法和装置
公开(公告)号：US08296709B2
公开(公告)日：2012-10-23
申请号：US13311996
申请日：2011-12-06
申请人： Vaughn Betz , Jordan Swartz , Vadim Gouterman
发明人： Vaughn Betz , Jordan Swartz , Vadim Gouterman
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.
摘要翻译：一种用于设计要在目标设备上实现的系统的方法包括在系统中为网络生成目标设备上的边界框，其中边界框标识可用于路由其相应网络的路由资源。系统中的网络被分配给要路由的多个线程。执行线程使得多个网络在其对应的边界框内并行路由。

74. 发明授权

US08271821B2 Flexible RAM clock enable 有权
标题翻译：灵活的RAM时钟使能
公开(公告)号：US08271821B2
公开(公告)日：2012-09-18
申请号：US12145440
申请日：2008-06-24
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

75. 发明授权

US08250500B1 Method and apparatus for deriving signal activities for power analysis and optimization 有权
标题翻译：用于导出功率分析和优化的信号活动的方法和装置
公开(公告)号：US08250500B1
公开(公告)日：2012-08-21
申请号：US11414803
申请日：2006-05-01
申请人： David Neto , Vaughn Betz , Jennifer Farrugia , Meghal Varia
发明人： David Neto , Vaughn Betz , Jennifer Farrugia , Meghal Varia
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for managing simulation includes modifying a design for a system to allow for a path pulse filter to filter a pathpulse delay, on a signal transmitted to a component, that is greater than an IOpath delay.
摘要翻译：一种用于管理仿真的方法包括修改系统的设计以允许路径脉冲滤波器对发送到组件的信号滤波大于IO路径延迟的路径脉冲延迟。

76. 发明授权

US07877555B1 Power-aware RAM processing 有权
标题翻译：电源感知RAM处理
公开(公告)号：US07877555B1
公开(公告)日：2011-01-25
申请号：US11510018
申请日：2006-08-24
申请人： Russell George Tessier , Vaughn Betz , Thiagaraja Golpalsamy , David Neto
发明人： Russell George Tessier , Vaughn Betz , Thiagaraja Golpalsamy , David Neto
IPC分类号： G06F12/00
CPC分类号： G11C5/14 , G11C7/22 , G11C8/12 , G11C2207/2227
摘要： Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.
摘要翻译：逻辑存储器和设计中指定的其他逻辑功能被映射到使用物理存储器和其他设备资源的功率优化实现。逻辑存储器可以自动映射到许多潜在的物理实现。对每个潜在的物理实现估计功耗，以选择在功耗和任何其他设计限制方面提供最佳性能的物理实现。当未访问嵌入式存储器时，潜在的物理实现可以通过时钟使能输入来抑制时钟转换。读使能和写使能信号可以转换为功能等效的时钟使能信号。可以创建时钟使能信号，以禁用未使用的存储器访问端口，并在不保养条件期间停用嵌入式存储器块。潜在的物理实现可以将逻辑存储器分解成两个或多个嵌入式存储器块，以最小化功耗。

77. 发明授权

US07737751B1 Periphery clock distribution network for a programmable logic device 有权
标题翻译：用于可编程逻辑器件的周边时钟分配网络
公开(公告)号：US07737751B1
公开(公告)日：2010-06-15
申请号：US11668521
申请日：2007-01-30
申请人： Gary Lai , Andy L. Lee , Ryan Fung , Vaughn Betz
发明人： Gary Lai , Andy L. Lee , Ryan Fung , Vaughn Betz
IPC分类号： H03K3/013
CPC分类号： G06F1/10
摘要： A programmable logic device (PLD) includes a signal distribution network, separate from the high-quality, low-skew clock distribution networks of the PLD, for distributing, from peripheral input/output regions of the PLD, clock-type signals. The signal distribution network includes a central periphery clock bus, located near a group of peripheral input/output regions, for conducting clock-type signals from those regions onto a clock spine of the PLD. The clock spine may be dedicated to the signal distribution network, or may be part of a high-quality, low-skew clock distribution network covering all or part of the PLD. The signal distribution network allows greater skew than such high-quality, low-skew clock distribution networks, but nevertheless is of higher quality, and allows less skew, than the general programmable interconnect and routing resources.
摘要翻译：可编程逻辑器件（PLD）包括与PLD的高质量，低偏移时钟分配网络分离的信号分配网络，用于从PLD的外围输入/输出区域分配时钟型信号。信号分配网络包括位于一组外围输入/输出区域附近的中央周边时钟总线，用于将这些区域的时钟信号传导到PLD的时钟脊上。时钟脊可以专用于信号分配网络，或者可以是覆盖全部或部分PLD的高质量，低偏移时钟分配网络的一部分。信号分配网络允许比这种高质量的低偏移时钟分配网络更大的偏斜，但是仍然具有比一般的可编程互连和路由资源更高的质量，并且允许较少的偏移。

78. 发明授权

US07629825B1 Efficient delay elements 有权
标题翻译：高效延时元件
公开(公告)号：US07629825B1
公开(公告)日：2009-12-08
申请号：US11549427
申请日：2006-10-13
申请人： Ryan Fung , Vaughn Betz
发明人： Ryan Fung , Vaughn Betz
IPC分类号： H03H11/26
CPC分类号： H03K19/17736 , H03K5/133 , H03K19/1778 , H03K19/17792 , H03K2005/00058 , H03K2005/00234
摘要： Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.
摘要翻译：提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

79. 发明申请

US20070101175A1 Systems and methods for reducing static and total power consumption in a programmable logic device 失效
公开(公告)号：US20070101175A1
公开(公告)日：2007-05-03
申请号：US11642287
申请日：2006-12-19
申请人： David Mendel , Vaughn Betz
发明人： David Mendel , Vaughn Betz
IPC分类号： G06F1/00
CPC分类号： G06F1/32
摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

80. 发明授权

US07194720B1 Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices 有权
标题翻译：用于在可编程逻辑器件上设计系统的工具中实现软约束的方法和装置
公开(公告)号：US07194720B1
公开(公告)日：2007-03-20
申请号：US10618416
申请日：2003-07-11
申请人： Terry P. Borer , Gabriel Quan , Stephen D. Brown , Deshanand P. Singh , Chris Sanford , Vaughn Betz , Caroline Pantofaru , Jordan Swartz
发明人： Terry P. Borer , Gabriel Quan , Stephen D. Brown , Deshanand P. Singh , Chris Sanford , Vaughn Betz , Caroline Pantofaru , Jordan Swartz
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5054
摘要： A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.
摘要翻译：利用可编程逻辑器件（PLD）在目标器件上设计系统的方法包括响应于用户指定的约束产生用于在PLD上利用资源的选项。独立于用户指定的约束，对PLD上资源的使用选项进行了细化。

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