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71. 发明申请

US20090309163A1 METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM AND DISCONTINUITY EXTENDING TO UNDERLYING LAYER 审中-公开
标题翻译：用于增强NMOSFET和PMOSFET性能的方法和结构，具有强化膜和延伸到下层的不连续性
公开(公告)号：US20090309163A1
公开(公告)日：2009-12-17
申请号：US12136970
申请日：2008-06-11
申请人： Jing Wang , Huilong Zhu
发明人： Jing Wang , Huilong Zhu
IPC分类号： H01L27/092 , H01L21/31
CPC分类号： H01L29/7843 , H01L21/3185 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L21/82385 , H01L21/823871
摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack. In an exemplary embodiment, the opening may be extended into an underlying layer such as a source/drain region of the shorter gate stack and a bottom thereof silicided such that a contact formed therein exhibits reduced contact resistance.
摘要翻译：用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。在示例性实施例中，开口可以延伸到下层，例如较短栅极堆叠的源极/漏极区域，并且其底部被硅化，使得其中形成的接触部显示出降低的接触电阻。

72. 发明授权

US07580567B2 Method and apparatus for two dimensional image processing 有权
标题翻译：二维图像处理方法和装置
公开(公告)号：US07580567B2
公开(公告)日：2009-08-25
申请号：US11473155
申请日：2006-06-21
申请人： Ming Hsieh , Huansheng Xue , Jing Wang , Chunyu Lu
发明人： Ming Hsieh , Huansheng Xue , Jing Wang , Chunyu Lu
IPC分类号： G06K9/00 , G06K9/60 , H04L12/66
CPC分类号： G06T1/60 , G06F17/18
摘要： In one embodiment, the present invention is a system for two dimensional digital image processing. The system includes a memory access module for accessing a memory containing image data to be processed, and a data flow organizer module for preparing a data stream from the input image data accessed by the memory access module. The data flow organizer module predicts future data needed for processing, and the memory access module pre-fetches the predicted data from the memory. A data processing module processes the pre-fetched data from the data flow organizer module. Address generation for accessing the memory is performed independent and in parallel with processing the pre-fetched data.
摘要翻译：在一个实施例中，本发明是用于二维数字图像处理的系统。该系统包括用于访问包含要处理的图像数据的存储器的存储器访问模块，以及用于由存储器访问模块访问的输入图像数据准备数据流的数据流管理器模块。数据流管理器模块预测处理所需的未来数据，并且存储器访问模块从存储器中预取预测数据。数据处理模块处理来自数据流管理器模块的预取数据。独立执行用于访问存储器的地址生成，并且与处理预取数据并行执行。

73. 发明申请

US20090127626A1 STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION 有权
标题翻译：应力生成具有双组分的浅层分离结构
公开(公告)号：US20090127626A1
公开(公告)日：2009-05-21
申请号：US11940531
申请日：2007-11-15
申请人： Huilong Zhu , Jing Wang
发明人： Huilong Zhu , Jing Wang
IPC分类号： H01L21/762 , H01L23/58 , H01L27/088
CPC分类号： H01L29/7846 , H01L21/3081 , H01L21/31053 , H01L21/76224 , H01L21/823807 , H01L21/823878 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.
摘要翻译：提供了一种浅沟槽隔离结构，其包含第一浅沟槽隔离部分，其包括第一浅沟槽材料和包括第二浅沟槽材料的第二浅沟槽隔离部分。在至少一个第二有效区域上的至少一个第一有效区域和第二双向应力上的第一双轴应力被分别操纵以通过选择第一和第二有源区域来增强至少一个第一和第二有源区域的中间部分中的载流子迁移率，第二浅沟槽材料以及调节所述至少一个第一有源区域和所述至少一个第二有源区域的每个部分横向邻接的浅沟槽隔离材料的类型。

74. 发明申请

US20080280285A1 Systems and Methods For Testing using Microfluidic Chips 审中-公开
标题翻译：使用微流控芯片进行测试的系统和方法
公开(公告)号：US20080280285A1
公开(公告)日：2008-11-13
申请号：US11937975
申请日：2007-11-09
申请人： Zongyuan G. Chen , Jing Wang , Michael Mauk , Haim H. Bau , Daniel Malamud , William Abrams , Raymond Niedbala , Hendrikus Johannes Tanke , Paul L.A.M. Corstjens
发明人： Zongyuan G. Chen , Jing Wang , Michael Mauk , Haim H. Bau , Daniel Malamud , William Abrams , Raymond Niedbala , Hendrikus Johannes Tanke , Paul L.A.M. Corstjens
IPC分类号： C12Q1/70 , B01J19/00 , C12M1/40 , C12Q1/04 , C12Q1/68 , C12P19/34 , C12M1/34 , G01N30/00 , C12M1/33 , G01N33/536 , G01N33/00
CPC分类号： G01N35/00029 , B01L3/502715 , B01L3/50273 , B01L3/502738 , B01L3/565 , B01L7/52 , B01L7/525 , B01L9/527 , B01L2200/10 , B01L2200/141 , B01L2200/143 , B01L2300/022 , B01L2300/0864 , B01L2300/1822 , B01L2400/0415 , B01L2400/0487 , B01L2400/0605 , B01L2400/0633 , B01L2400/0672 , B01L2400/0677 , B01L2400/0688 , G01N2035/00158 , Y10T436/143333
摘要： Disclosed are methods, devices and systems for biological and chemical sample processing using microfluidic chips. The disclosed microfluidic chips contain at least two detection zones for interacting with pre-selected RNA sequences, DNA sequences, antibodies, or antigens to determine their presence in the sample. Systems are also described comprising a cassette having at least one port and a sample inlet in fluid communication with a detection zone for interacting with pre-selected RNA sequences, DNA sequences, antibodies, or antigens, or mixtures thereof, if present, in a sample. Methods for concurrent testing of at least two of RNA, DNA, antibody, and antigen in a sample are also described, as are methods for testing for pre-selected pathogens and microfluidic methods.
摘要翻译：公开了使用微流控芯片的生物和化学样品处理的方法，装置和系统。所公开的微流控芯片包含至少两个用于与预先选择的RNA序列，DNA序列，抗体或抗原相互作用的检测区域，以确定它们在样品中的存在。还描述了系统，其包括具有至少一个端口的盒和与检测区流体连通的样品入口，用于与样品中预先选择的RNA序列，DNA序列，抗体或抗原或其混合物（如果存在）相互作用。还描述了样品中至少两种RNA，DNA，抗体和抗原的同时测试方法，以及用于测试预先选择的病原体和微流体方法的方法。

75. 外观设计

USD573659S1 Dancing pad for online gaming application 有权
标题翻译：用于在线游戏应用的跳舞垫
公开(公告)号：USD573659S1
公开(公告)日：2008-07-22
申请号：US29247467
申请日：2006-06-20
申请人： Jing Wang
设计人： Jing Wang

76. 发明授权

US07381736B2 Thiazole and thiadiazole inhibitors of tyrosine phosphatases 失效
标题翻译：噻唑和噻二唑抑制剂酪氨酸磷酸酶
公开(公告)号：US07381736B2
公开(公告)日：2008-06-03
申请号：US11219402
申请日：2005-09-02
申请人： Zacharia S. Cheruvallath , Colin J. Loweth , Ruth F. Nutt , Darryl Rideout , Joseph E. Semple , Jing Wang , Feiyue Wu , Shankari Mylvaganam , Hengyi Zhu , Jianzhong Sun
发明人： Zacharia S. Cheruvallath , Colin J. Loweth , Ruth F. Nutt , Darryl Rideout , Joseph E. Semple , Jing Wang , Feiyue Wu , Shankari Mylvaganam , Hengyi Zhu , Jianzhong Sun
IPC分类号： A61K31/427 , C07D277/18
CPC分类号： C07D277/38 , C07D277/42 , C07D285/135 , C07D417/12 , C07D417/14 , C07F9/6539 , C07F9/65395
摘要： Compounds and compositions are provided for modulating the activity of protein tyrosine phosphatases. In one embodiment, the compounds and compositions are thiazoles and thiadiazoles that inhibit the activity of protein tyrosine phosphatase 1B.
摘要翻译：提供化合物和组合物用于调节蛋白酪氨酸磷酸酶的活性。在一个实施方案中，化合物和组合物是抑制蛋白酪氨酸磷酸酶1B活性的噻唑和噻二唑。

77. 发明申请

US20080107578A1 THE RECOVERY OF ALUMINA TRIHYDRATE DURING THE BAYER PROCESS USING A WATER CONTINUOUS POLYMER 审中-公开
标题翻译：使用水连续聚合物在贝氏过程中恢复三氧化二铝
公开(公告)号：US20080107578A1
公开(公告)日：2008-05-08
申请号：US11557341
申请日：2006-11-07
申请人： Jing Wang , Kevin L. O'Brien , Michael G. Strominger , David C. Davis
发明人： Jing Wang , Kevin L. O'Brien , Michael G. Strominger , David C. Davis
IPC分类号： C01F1/00
CPC分类号： C01F7/148 , C01P2004/50
摘要： A method for increasing the floccule size and volume of alumina trihydrate during the Bayer processing of bauxite ore using a flocculant in conjunction with a water continuous polymer. The addition of the flocculant and the water continuous polymer to the alumina trihydrate slurry following the security filtration and settling producing trihydrate that is put through the calcination process to produce purified alumina or used as seed for the precipitation process.
摘要翻译：在使用絮凝剂与水连续聚合物结合的铝土矿矿石的拜耳处理中，增加矾土三水合物的絮凝物尺寸和体积的方法。在安全过滤和沉降生成三水合物之后，将絮凝剂和水连续聚合物加入到三水合氧化铝浆料中，通过煅烧过程产生纯化的氧化铝或用作沉淀过程的种子。

78. 发明申请

US20070129364A1 Pyrrolopyridine kinase inhibiting compounds 审中-公开
标题翻译：吡咯并吡啶激酶抑制化合物
公开(公告)号：US20070129364A1
公开(公告)日：2007-06-07
申请号：US11634003
申请日：2006-12-05
申请人： Han-Qing Dong , Kenneth Foreman , An-Hu Li , Mark Mulvihill , Bijoy Panicker , Arno Steinig , Kathryn Stolz , Qinghua Weng , Meizhong Jin , Brian Volk , Jing Wang , Ti Wang , James Beard
发明人： Han-Qing Dong , Kenneth Foreman , An-Hu Li , Mark Mulvihill , Bijoy Panicker , Arno Steinig , Kathryn Stolz , Qinghua Weng , Meizhong Jin , Brian Volk , Jing Wang , Ti Wang , James Beard
IPC分类号： A61K31/5377 , A61K31/496 , A61K31/4745 , C07D471/02
CPC分类号： C07D471/04
摘要： Compounds represented by Formula (I): or stereoisomers or pharmaceutically acceptable salts thereof, are inhibitors of least one of the Abl, Aurora-A, Blk, c-Raf, cSRC, Src, PRK2, FGFR3, Flt3, Lck, Mek1, PDK-1, GSK3β, EGFR, p70S6K, BMX, SGK, CaMKII, Tie-2, IGF-1R, Ron, Met, and KDR kinases in animals, including humans, for the treatment and/or prevention of various diseases and conditions such as cancer.
摘要翻译：由式（I）表示的化合物或其立体异构体或其药学上可接受的盐是Abl，Aurora-A，Blk，c-Raf，cSRC，Src，PRK2，FGFR3，Flt3，Lck，Mek1，PDK中的至少一种的抑制剂 -1，GSK3beta，EGFR，p70S6K，BMX，SGK，CaMKII，Tie-2，IGF-1R，Ron，Met和KDR激酶，用于治疗和/或预防各种疾病和病症，癌症。

79. 发明申请

US20070122961A1 METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WITH A STRESSED FILM 有权
标题翻译：用于增强半导体场效应晶体管的NMOSFET和PMOSFET性能的方法和结构
公开(公告)号：US20070122961A1
公开(公告)日：2007-05-31
申请号：US11560925
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
IPC分类号： H01L21/8234 , H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

80. 发明申请

US20070120197A1 METHOD AND STRUCTURE FOR ENHANCING BOTH NMOSFET AND PMOSFET PERFORMANCE WTH A STRESSED FILM 有权
标题翻译：用于增强NMOSFET和PMOSFET性能的方法和结构WTH A受压膜
公开(公告)号：US20070120197A1
公开(公告)日：2007-05-31
申请号：US11561047
申请日：2006-11-17
申请人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
发明人： Huilong Zhu , Jing Wang , Bruce Doris , Zhibin Ren
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L29/6653 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.
摘要翻译：用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口使得在较短的栅极堆叠下形成第二种类型的应力。

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