会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 73. 发明授权
    • Resource management device for managing access from bus masters to shared resources
    • 用于管理从总线主机访问共享资源的资源管理设备
    • US07032046B2
    • 2006-04-18
    • US10673191
    • 2003-09-30
    • Seiji HoriiYuji TakaiTakahide BabaYoshiharu WatanabeDaisuke MurakamiTetsuji Kishi
    • Seiji HoriiYuji TakaiTakahide BabaYoshiharu WatanabeDaisuke MurakamiTetsuji Kishi
    • G06F13/36
    • G06F13/1663
    • A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.
    • 本发明的资源管理装置用于至少一个总线主机连接到多个总线中的每一个的系统中,包括:总线仲裁部,用于将从总线进行的访问量仲裁为共享 资源; 仲裁信息管理部分,用于作为总线仲裁信息,用于总线优先权顺序和最高访问优先级模式,用于确保每个总线的共享资源的预定访问带宽用于总线仲裁部分的仲裁操作; 以及资源控制部分,用于基于所述共享资源的特性,从总线仲裁部分已经授权其访问请求的总线访问共享资源。 因此,可以保证用于访问多个总线主机中的每一个的共享资源的最小带宽。
    • 75. 发明授权
    • Pulse signal generator and cascode differential amplifier
    • 脉冲信号发生器和同步差分放大器
    • US5191234A
    • 1993-03-02
    • US803992
    • 1991-12-09
    • Daisuke MurakamiTadao Kuwabara
    • Daisuke MurakamiTadao Kuwabara
    • H03K5/00H03K5/13
    • H03K5/131H03K5/133H03K2005/00097H03K2005/00176H03K2005/00182H03K2005/00228
    • A pulse signal generator comprising a plurality of stages of delay gates connected in series to one another for delaying input signals fed to input terminals; first differential connection circuits interposed respectively between the stages of the delay gates so as to transmit, at a predetermined timing, the signals passed through the delay gates; first and second input lines for supplying the output signals of the first differential connection circuits to a cascode amplifier; and second differential connection circuits each consisting of a pair of transistors which are supplied with the same input signals as those fed to each pair of transistors constituting the first differential connection circuit, wherein the second differential connection circuit is connected to the first and second input lines in such a manner that the outputs of the transistors thereof become inverse in polarity to the outputs of the transistors of the corresponding first differential connection circuit. The pulse signal generator is capable of reducing a formable minimum pulse duration while suppressing occurrence of jitters even in a superhigh-speed operation. And its prevents delay time variations that may otherwise be caused by variations in the values of resistors formed in an integrated circuit, thereby maintaining the signal delay time constant per delay gate.
    • 一种脉冲信号发生器,包括彼此串联连接的多级延迟门,用于延迟馈送到输入端的输入信号; 第一差分连接电路分别插入延迟门的级之间,以便在预定定时传送通过延迟门的信号; 第一和第二输入线,用于将第一差分连接电路的输出信号提供给共源共栅放大器; 以及第二差分连接电路,每个由一对晶体管构成,所述晶体管被提供有与馈送到构成第一差分连接电路的每对晶体管的馈入相同的输入信号,其中第二差分连接电路连接到第一和第二输入线 使得晶体管的输出极性与相应的第一差分连接电路的晶体管的输出相反。 脉冲信号发生器即使在超高速操作中也能够抑制可形成的最小脉冲持续时间,同时抑制抖动的发生。 并且其防止可能由集成电路中形成的电阻器的值的变化引起的延迟时间变化,从而保持每个延迟门的信号延迟时间常数。
    • 76. 发明授权
    • Programmable delay circuit having n-stage capacitance elements
    • 具有n级电容元件的可编程延迟电路
    • US5175454A
    • 1992-12-29
    • US838888
    • 1992-02-21
    • Daisuke Murakami
    • Daisuke Murakami
    • H03K5/00H03K5/13
    • H03K5/131H03K5/133H03K2005/00052H03K2005/00169H03K2005/00176H03K2005/00228
    • A programmable delay circuit comprising input terminals supplied with input signals to be delayed; output terminals for delivering the delayed signals therefrom; resistance elements inserted between the input terminals and the output terminals; n-stage capacitance elements having capacitance values of C, ZC, 4C . . . 2.sup.n-1 C respectively (where C is a unit capacitance value) and each connected at one end thereof to the output ends of the resistance elements; and n-stage selection means for selectively applyign to the other ends of the n-stage capacitance elements either a signal having an opposite-phase or in-phase relation to the input signal, or a reference potential level. The delay circuit is capable of performing a control operation relative to any short delay time on the order of picosecond and still ensuring satisfactory linearity in the delay characteristics.
    • 一种可编程延迟电路,包括输入端提供有待延迟的输入信号; 用于从其输送延迟信号的输出端; 插入在输入端子和输出端子之间的电阻元件; 电容值为C,ZC,4C的n段电容元件。 。 。 2n-1C(其中C是单位电容值),并且其一端分别连接到电阻元件的输出端; 以及n级选择装置,用于选择性地将n级电容元件的另一端施加到与输入信号具有相位或同相关系的信号或参考电位电平。 延迟电路能够执行相对于微秒级的任何短延迟时间的控制操作,并且仍然确保延迟特性中令人满意的线性度。