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71. 发明申请

US20080173976A1 AIR GAP UNDER ON-CHIP PASSIVE DEVICE 有权
标题翻译：在片上被动设备上的空气隙
公开(公告)号：US20080173976A1
公开(公告)日：2008-07-24
申请号：US11626548
申请日：2007-01-24
申请人： Anthony K. Stamper , Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , William J. Murphy , Kunal Vaed
发明人： Anthony K. Stamper , Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , William J. Murphy , Kunal Vaed
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L27/0688 , H01L21/7682 , H01L23/5222 , H01L23/5227 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.
摘要翻译：提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。形成无源器件至少覆盖第一ILD层。使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

72. 发明申请

US20080164613A1 ULTRA-THIN Cu ALLOY SEED FOR INTERCONNECT APPLICATION 审中-公开
标题翻译：超细铜合金用于互连应用
公开(公告)号：US20080164613A1
公开(公告)日：2008-07-10
申请号：US11621709
申请日：2007-01-10
申请人： Daniel C. Edelstein , Stephen M. Rossnagel
发明人： Daniel C. Edelstein , Stephen M. Rossnagel
IPC分类号： H01L23/48 , H01L21/288
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： A copper interconnection structure which is electroplated onto a silicon layer or semiconductor substrate. The structure includes an ultra-thin copper seed alloy incorporating selectively minor amounts of a dopant material to facilitate a continuous deposition thereof onto the silicon layer or semiconductor substrate. The copper seed alloy may contain dopant material selected from the group of materials consisting of Ru, Ir, Pt, Pd and alloys thereof. Furthermore, there is provided a method for producing the structure.
摘要翻译：电镀在硅层或半导体衬底上的铜互连结构。该结构包括超薄铜种子合金，其选择性地少量掺杂材料，以促进其连续沉积到硅层或半导体衬底上。铜种子合金可以含有选自由Ru，Ir，Pt，Pd及其合金组成的材料组的掺杂剂材料。此外，提供了一种制造该结构的方法。

73. 发明申请

US20080132027A1 PLANAR VERTICAL RESISTOR AND BOND PAD RESISTOR AND RELATED METHOD 失效
标题翻译：平面垂直电阻和焊盘电阻及相关方法
公开(公告)号：US20080132027A1
公开(公告)日：2008-06-05
申请号：US11954782
申请日：2007-12-12
申请人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
发明人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L23/5228 , H01L23/53238 , H01L23/53295 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要翻译：公开了避免半导体器件小型化的问题的电阻器及相关方法。在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。这两个实施方案可以单独使用或一起使用。还公开了用于产生电阻器的相关方法。

74. 发明申请

US20080122106A1 Method to generate airgaps with a template first scheme and a self aligned blockout mask 有权
标题翻译：使用模板第一方案和自对准遮挡掩码生成气隙的方法
公开(公告)号：US20080122106A1
公开(公告)日：2008-05-29
申请号：US11518773
申请日：2006-09-11
申请人： Satyanarayana Venkata Nitta , Sampath Purushothaman , Matthew E. Colburn , Daniel C. Edelstein , Shom Poncth
发明人： Satyanarayana Venkata Nitta , Sampath Purushothaman , Matthew E. Colburn , Daniel C. Edelstein , Shom Poncth
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/7682
摘要： A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.
摘要翻译：在具有转印到电介质层上的图案的电介质层和在图案周围的电介质层上转移的自对准阻挡掩模的衬底上产生气隙的结构和方法。

75. 发明授权

US07273770B2 Compliant passivated edge seal for low-k interconnect structures 有权
标题翻译：符合低k互连结构的钝化边缘密封
公开(公告)号：US07273770B2
公开(公告)日：2007-09-25
申请号：US11464959
申请日：2006-08-16
申请人： Daniel C. Edelstein , Lee M. Nicholson
发明人： Daniel C. Edelstein , Lee M. Nicholson
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44 , H01L23/31
CPC分类号： H01L23/3135 , H01L23/3121 , H01L23/3178 , H01L23/3185 , H01L2924/00013 , H01L2924/0002 , H01L2924/1433 , H01L2924/19041 , H01L2224/29099 , H01L2924/00
摘要： A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.
摘要翻译：公开了一种用于芯片或芯片封装的结构，其具有机械去耦合但电耦合到多层片上互连的最终钝化和终端冶金。这种去耦允许芯片在最终钝化区域中经受包装应力，在去耦区域和柔性引线处具有应变消除，使得片上互连电平不会感受到这些外部封装或其他应力。对于由Cu和低k电介质组成的片上互连，该结构特别优选，后者相对于SiO 2具有差的机械性能。去耦区延伸在晶片上的所有芯片上。它也可以延伸到edgeseal或切割通道区域，以便允许在晶片上的每个芯片周围进行芯片切割和保持这种机械解耦。

76. 发明授权

US07119018B2 Copper conductor 有权
公开(公告)号：US07119018B2
公开(公告)日：2006-10-10
申请号：US10887087
申请日：2004-07-09
申请人： Michael W. Lane , Stefanie R. Chiras , Terry A. Spooner , Robert Rosenberg , Daniel C. Edelstein
发明人： Michael W. Lane , Stefanie R. Chiras , Terry A. Spooner , Robert Rosenberg , Daniel C. Edelstein
IPC分类号： H01L21/44
CPC分类号： C25D5/10 , C25D5/50 , C25D7/123 , H01L21/2885 , H01L21/76807 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76886 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

77. 发明授权

US07084079B2 Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications 失效
公开(公告)号：US07084079B2
公开(公告)日：2006-08-01
申请号：US10299357
申请日：2002-11-18
申请人： Richard A. Conti , Daniel C. Edelstein , Gill Yong Lee
发明人： Richard A. Conti , Daniel C. Edelstein , Gill Yong Lee
IPC分类号： H01L21/469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02112 , H01L21/02129 , H01L21/02205 , H01L21/02216 , H01L21/3122 , H01L21/31604 , H01L21/31625 , H01L21/31629 , H01L21/31633 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

78. 发明授权

US07030031B2 Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material 有权
标题翻译：使用与扩散阻挡材料耦合的平面化材料形成镶嵌结构的方法
公开(公告)号：US07030031B2
公开(公告)日：2006-04-18
申请号：US10604056
申请日：2003-06-24
申请人： William C. Wille , Daniel C. Edelstein , William J. Cote , Peter E. Biolsi , John Fritche , Allan W. Upham
发明人： William C. Wille , Daniel C. Edelstein , William J. Cote , Peter E. Biolsi , John Fritche , Allan W. Upham
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76804
摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.
摘要翻译：本发明涉及集成电路器件中的双镶嵌互连结构的制造。具体地，公开了一种利用平面化材料和扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。然后可以将所得的双镶嵌结构金属化。通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

79. 发明授权

US06740539B2 Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates 有权
标题翻译：碳分级层，用于改善低k电介质与硅衬底的粘附性
公开(公告)号：US06740539B2
公开(公告)日：2004-05-25
申请号：US10366149
申请日：2003-02-13
申请人： Richard A. Conti , Prakash Chimanlal Dev , David M. Dobuzinsky , Daniel C. Edelstein , Gill Y. Lee , Kia-Seng Low , Padraic C. Shafer , Alexander Simpson , Peter Wrschka
发明人： Richard A. Conti , Prakash Chimanlal Dev , David M. Dobuzinsky , Daniel C. Edelstein , Gill Y. Lee , Kia-Seng Low , Padraic C. Shafer , Alexander Simpson , Peter Wrschka
IPC分类号： H01L5140
CPC分类号： H01L21/28185 , H01L21/02126 , H01L21/02274 , H01L21/28194 , H01L21/31633 , H01L23/5329 , H01L23/53295 , H01L29/513 , H01L29/517 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.
摘要翻译：公开了一种在衬底上方具有碳分级层的绝缘体层的结构和方法，其中在衬底上方的每个连续的碳分级层中碳的浓度增加。绝缘体包括介电常数小于3.3的低k电介质。碳分级层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘合性。该结构还可以包括碳分级层之间的稳定界面。更具体地，碳分级层包括邻近基底的第一层，其碳含量在约5％至20％之间，第一层上方的碳含量在约10％至30％之间，第三层在第二层上方具有约20％至40％的碳含量。

80. 发明授权

US06647614B1 Method for changing an electrical resistance of a resistor 失效
标题翻译：改变电阻器电阻的方法
公开(公告)号：US06647614B1
公开(公告)日：2003-11-18
申请号：US09693765
申请日：2000-10-20
申请人： Arne W. Ballantine , Cyril Cabral, Jr. , Daniel C. Edelstein , Anthony K. Stamper
发明人： Arne W. Ballantine , Cyril Cabral, Jr. , Daniel C. Edelstein , Anthony K. Stamper
IPC分类号： H01C1700
CPC分类号： H01L28/20 , H01C7/006 , H01C17/242 , Y10T29/49082 , Y10T29/49099 , Y10T29/49105
摘要： A method for changing an electrical resistance of a resistor. Initially, the resistor is provided, wherein the resistor has a length L and an electrical resistance R1. A portion of the resistor is exposed to a laser radiation, wherein the portion includes a fraction F of the length L of the resistor. After the resistor has been exposed to the laser radiation, the resistor has an electrical resistance R2, wherein R2 is unequal to R1.
摘要翻译：一种改变电阻器电阻的方法。首先，提供电阻器，其中电阻器具有长度L和电阻R1。电阻器的一部分暴露于激光辐射，其中该部分包括电阻器长度L的分数F. 在电阻器暴露于激光辐射之后，电阻器具有电阻R2，其中R2不等于R1。

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