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71. 发明授权

US06710735B1 Dual supply voltage pipelined ADC 有权
标题翻译：双电源电压流水线ADC
公开(公告)号：US06710735B1
公开(公告)日：2004-03-23
申请号：US10464718
申请日：2003-06-17
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03M138
CPC分类号： H03M1/089 , H03M1/167 , H03M1/44
摘要： An analog-to-digital converter (ADC) includes N stages implemented within a single integrated circuit and connected in series to form a pipeline. The first stage of the pipeline receives the analog signal as its input, and each of the first N−1 stages of the pipeline supplies an analog residue signal as input to a next succeeding stage of the pipeline. Each stage includes an amplifier for amplifying its input signal to produce a sample voltage stored in an internal sampling capacitor and generates output data indicating an approximate magnitude of its stored sample voltage. The magnitude of the analog residue signal produced by each stage indicates a difference between the voltage represented by that stage's output data and its sample voltage. The amplifiers of the first N-M stages of the pipeline are powered by a higher supply voltage than the amplifiers of the last M stages of the pipeline to maximize the sample voltages in the first N-M stages, thereby reducing the influence of thermal noise on the sample voltages in those stages.
摘要翻译：模数转换器（ADC）包括在单个集成电路内实现并且串联连接以形成管线的N级。管线的第一级接收模拟信号作为其输入，并且流水线的第一N-1级中的每一级将模拟残留信号作为输入提供给管道的下一级。每个级包括用于放大其输入信号以产生存储在内部采样电容器中的采样电压的放大器，并产生指示其存储的采样电压的近似幅度的输出数据。每级产生的模拟残留信号的大小表示由该级输出数据表示的电压与其采样电压之间的差值。管道的第一NM级的放大器由比管道的最后M级的放大器更高的电源电压供电，以使第一NM级中的采样电压最大化，从而减少热噪声对采样电压的影响在这些阶段。

72. 发明授权

US06642874B1 Sigma-delta data conversion employing quantization error feedback 有权
标题翻译：采用量化误差反馈的Sigma-delta数据转换
公开(公告)号：US06642874B1
公开(公告)日：2003-11-04
申请号：US10269594
申请日：2002-10-11
申请人： Chia-Liang Lin , Tzu-Hsien Sang
发明人： Chia-Liang Lin , Tzu-Hsien Sang
IPC分类号： H03M300
CPC分类号： H03M7/3008 , H03M3/326 , H03M3/458 , H03M7/3024
摘要： A sigma-delta circuit converts an analog or digital input sequence xn representing a quantity with at least p-bit resolution into an m-bit output sequence yn, where m
摘要翻译： Σ-Δ电路将表示具有至少p位分辨率的量的模拟或数字输入序列xn转换成m位输出序列yn，其中m

73. 发明授权

US09214945B2 Digital phase lock loop and method thereof 有权
标题翻译：数字锁相环及其方法
公开(公告)号：US09214945B2
公开(公告)日：2015-12-15
申请号：US13405927
申请日：2012-02-27
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03L7/06 , H03L7/087 , H03L7/099 , H03L7/10
CPC分类号： H03L7/087 , H03L7/099 , H03L7/101 , H03L2207/50
摘要： An apparatus of digital phase lock loop and method are provided. In one embodiment, an apparatus comprises: an analog-to-digital converter (ADC) for converting a voltage level of an output clock into a first digital word in accordance with a timing defined by a reference clock; a first digital loop filter for receiving the first digital word and outputting a control code; a circuit to receive the reference clock and the output clock and output an offset code according to a frequency error of the output clock with respect to a frequency of the reference clock; an adder for generating an offset control code by summing the control code with the offset code; and a digitally controlled oscillator for outputting the output clock in accordance with the offset control code.
摘要翻译：提供了数字锁相环和装置的方法。在一个实施例中，一种装置包括：模数转换器（ADC），用于根据由参考时钟定义的定时将输出时钟的电压电平转换成第一数字字; 第一数字环路滤波器，用于接收第一数字字并输出控制码; 接收参考时钟和输出时钟的电路，并根据输出时钟相对于参考时钟的频率的频率误差输出偏移码; 加法器，用于通过将控制码与偏移码相加来产生偏移控制代码; 以及用于根据偏移控制代码输出输出时钟的数字控制振荡器。

74. 发明授权

US09083299B2 Filter of adjustable frequency response and method thereof 有权
标题翻译：可调频率响应滤波器及其方法
公开(公告)号：US09083299B2
公开(公告)日：2015-07-14
申请号：US11553452
申请日：2006-10-26
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03D5/00 , H04B1/18 , H04B1/16 , H03H2/00
CPC分类号： H03H2/00 , H03H2250/00
摘要： A filter of an adjustable frequency response comprises a plurality of filters having a plurality of distinct frequency responses, respectively. These filters receive a common input signal and generate a plurality of intermediate signals, respectively. A multiplexing circuit is used to select one of these intermediate signals as a filtered signal. The multiplexing circuit is controlled by a control signal that is related to a state of the filtered signal.
摘要翻译：可调频率响应的滤波器分别包括具有多个不同频率响应的多个滤波器。这些滤波器接收公共输入信号并分别产生多个中间信号。复用电路用于选择这些中间信号之一作为滤波信号。复用电路由与滤波信号的状态有关的控制信号控制。

75. 发明授权

US08854028B2 Signal level detector and method thereof 有权
标题翻译：信号电平检测器及其方法
公开(公告)号：US08854028B2
公开(公告)日：2014-10-07
申请号：US13299594
申请日：2011-11-18
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： G05F3/04 , H03K19/0175 , H04B17/00
CPC分类号： H03K19/0175 , H03F3/45183 , H03F3/45237
摘要： A signal level detector and detecting method are provided. In one implementation a method includes receiving a differential input signal; incorporating two configurable rectifiers of the same circuit topology; configuring a first one of the two configurable rectifiers as a inverting rectifier to generate an inverting end of an output signal in response to an absolute value of the differential input signal; and configuring a second one of the two configurable rectifiers as a non-inverting rectifier to generate a non-inverting end of the output signal.
摘要翻译：提供信号电平检测器和检测方法。在一个实现中，一种方法包括：接收差分输入信号; 并入两个相同电路拓扑的可组态整流器; 将两个可配置整流器中的第一个配置为反相整流器，以响应于差分输入信号的绝对值产生输出信号的反相端; 以及将所述两个可配置整流器中的第二个配置为非反相整流器以产生所述输出信号的非反相端。

76. 发明授权

US08570111B2 Single-staged balanced-output inductor-free oscillator and method thereof 有权
标题翻译：单级平衡输出电感自由振荡器及其方法
公开(公告)号：US08570111B2
公开(公告)日：2013-10-29
申请号：US13287960
申请日：2011-11-02
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03K3/354
CPC分类号： H03B5/24 , H03B2200/0036
摘要： A single-staged balanced-output inductor-free oscillator and method thereof are provided. In one implementation an apparatus includes a first network comprising a first amplifier configured in a self feedback topology via a first feedback network for generating a first end of an output signal; a second network comprising a second amplifier configured in a self feedback topology via a second feedback network for generating a second end of the output signal; and a cross-coupling network for cross-coupling the first end and the second end of the output signal, wherein the first network and the second network share a common supply current and the first feedback network and the second feedback network are configured in a cross-controlling topology.
摘要翻译：提供了一种单级平衡输出无电感振荡器及其方法。在一个实现中，装置包括第一网络，其包括经由第一反馈网络配置在自反馈拓扑中的第一放大器，用于产生输出信号的第一端; 第二网络，包括经由第二反馈网络配置在自反馈拓扑中的第二放大器，用于产生所述输出信号的第二端; 以及用于交叉耦合输出信号的第一端和第二端的交叉耦合网络，其中第一网络和第二网络共享公共供电电流，并且第一反馈网络和第二反馈网络被配置为交叉控制拓扑。

77. 发明授权

US08283984B2 Method and apparatus of phase locking for reducing clock jitter due to charge leakage 有权
标题翻译：用于减少由于电荷泄漏引起的时钟抖动的锁相方法和装置
公开(公告)号：US08283984B2
公开(公告)日：2012-10-09
申请号：US12830317
申请日：2010-07-03
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/0891
摘要： A phase lock loop is disclosed comprising a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal.
摘要翻译：公开了一种锁相环，包括：第一相位检测器，被配置为接收第一时钟和第二时钟并输出第一检测器输出信号; 第二相位检测器，被配置为接收第一时钟和第二时钟并输出第二检测器输出信号; 求和电路，用于将第一检测器输出信号和第二检测器输出信号合并为控制信号; 环路滤波器，用于将控制信号滤波成精细的控制信号; 以及可控振荡器，以根据精细控制信号的控制产生输出时钟。

78. 发明授权

US08255449B2 High-speed continuous-time fir filter 有权
标题翻译：高速连续冷杉过滤器
公开(公告)号：US08255449B2
公开(公告)日：2012-08-28
申请号：US12421647
申请日：2009-04-10
申请人： Chia-Liang Lin , Hsin-Che Chiang
发明人： Chia-Liang Lin , Hsin-Che Chiang
IPC分类号： G06G7/02
CPC分类号： H04L25/03012 , H03H11/1291
摘要： A high-speed continuous-time FIR (finite impulse response) filter comprises a plurality of processing cells configured in a cascade topology. Each processing cell receives a first signal and a second signal from a preceding circuit and a succeeding circuit, respectively, and outputs a third signal and a fourth signal to the succeeding circuit and the preceding circuit, respectively. Each processing cell further comprises a delay cell and a summing cell. Each of the delay cell and the summing cell performs a high speed signal processing using a combination of a feedback loop and a feedforward path.
摘要翻译：高速连续时间FIR（有限脉冲响应）滤波器包括以级联拓扑结构配置的多个处理单元。每个处理单元分别从前一电路和后续电路接收第一信号和第二信号，并分别向后续电路和先前电路输出第三信号和第四信号。每个处理单元还包括延迟单元和求和单元。延迟单元和求和单元中的每一个使用反馈回路和前馈路径的组合来执行高速信号处理。

79. 发明授权

US07769121B2 Phase detector for data communications 有权
标题翻译：用于数据通信的相位检测器
公开(公告)号：US07769121B2
公开(公告)日：2010-08-03
申请号：US11315029
申请日：2005-12-22
申请人： Chia-Liang Lin
发明人： Chia-Liang Lin
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03D13/003 , H03L7/0891 , H03L7/091
摘要： In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be based on suppressing the low frequency components of the phase error signal. For example, the amplitude of the phase error signal may be reduced when the amplitude of the phase error signal is not changing.
摘要翻译：在一个实施例中，由相位检测器产生的相位误差信号被均衡以补偿由于有限电路速度引起的相位误差信号中的失真。均衡可以基于抑制相位误差信号的低频分量。例如，当相位误差信号的振幅不变时，相位误差信号的幅度可能会降低。

80. 发明授权

US07693225B2 Inter-symbol and inter-carrier interference canceller for multi-carrier modulation receivers 有权
标题翻译：用于多载波调制接收机的符号间和载波间干扰消除器
公开(公告)号：US07693225B2
公开(公告)日：2010-04-06
申请号：US11256707
申请日：2005-10-24
申请人： Chia-Liang Lin , Heng-Cheng Yeh , Cheng-Hsian Li
发明人： Chia-Liang Lin , Heng-Cheng Yeh , Cheng-Hsian Li
IPC分类号： H04K1/10
CPC分类号： H04L25/03159 , H04L27/2601 , H04L2025/03414
摘要： A MCM (multi-carrier modulation) receiver that utilizes a plurality tones to transmit information. Identify a first subset of tones that have negligible ISI (inter-symbol interference) and ICI (inter-carrier interference), and a second subset of tones that ISI/ICI cancellation is needed to improve the performance. For tones in the first subset, conventional FEQ (frequency-domain equalization) is performed to obtained soft decisions from the raw decisions. For those tones in the second subset, perform FEQ along with ICI/ISI cancellation. For tones in the second subset, identify a third subset (one for each of the tones in the second subset) to perform ICI cancellation and a series of fourth subsets (one for each of the tones in the second subset) to perform ISI cancellation. The selection of the first subset, the second subset, the third subset (for each of the tone in the second subset), and the fourth subset (for each of the tone in the second subset) are based on examining the frequency response of the communication channel.
摘要翻译：利用多个音调传送信息的MCM（多载波调制）接收机。识别具有可忽略的ISI（符号间干扰）和ICI（载波间干扰）的第一个音调子集，以及需要ISI / ICI取消的第二个音调子集来提高性能。对于第一子集中的音调，执行常规FEQ（频域均衡）以从原始决策获得软判决。对于第二个子集中的那些音调，执行FEQ以及ICI / ISI取消。对于第二子集中的音调，识别第三子集（一个用于第二子集中的每个音调）以执行ICI消除和一系列第四子集（一个用于第二子集中的每个音调）以执行ISI取消。基于检查第一子集，第二子集，第三子集（对于第二子集中的每个音调）和第四子集（对于第二子集中的每个音调）的选择，沟通渠道

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