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71. 发明授权

US08112574B2 Swappable sets of partial-mapping tables in a flash-memory system with a command queue for combining flash writes 有权
标题翻译：具有用于组合闪存写入的命令队列的闪存系统中的可转换的部分映射表
公开(公告)号：US08112574B2
公开(公告)日：2012-02-07
申请号：US12347306
申请日：2008-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G11C16/102 , G11C2216/30
摘要： A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.
摘要翻译：闪存控制器具有访问多电平单元（MLC）闪存的物理块的闪存接口。扩展通用串行总线（EUSB）接口将主机命令加载到命令队列中，其中写入被重新排序并组合以减少闪存写入。 RAM中的部分逻辑到物理L2P映射表仅具有N组L2P映射表中的1个的条目。其他N-1组存储在闪存中，并在发生L2P表错误时被提取到RAM中。映射所需的RAM大大降低。数据缓冲器存储一页主机写入数据。扇区写入使用数据缓冲区进行合并。当写入不同的页面时，数据缓冲区被刷新闪存，而当L2P表错过发生时，部分逻辑到物理映射表被刷新为闪存，当主机地址是N组的L2P中的不同的一个映射表。

72. 发明申请

US20090240873A1 Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System 有权
标题翻译：闪存系统的多级条带和截断信道均衡
公开(公告)号：US20090240873A1
公开(公告)日：2009-09-24
申请号：US12475457
申请日：2009-05-29
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
IPC分类号： G06F12/00 , G06F12/02 , H03M13/00
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0631 , G06F3/0688 , G06F2212/7203 , G06F2212/7208 , G11C11/5678 , G11C13/0004 , G11C29/765
摘要： Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.
摘要翻译：截断将所有闪存通道的可用条带数据容量减小到最小闪存通道的容量。固态磁盘（SSD）具有智能存储交换机，通过截断来保护从条带数据容量中移除的闪存存储。超出条带数据容量的额外存储被访问为不带条纹的分散数据。随着更多的坏块出现，条带数据容量的大小随着时间的推移而减少。一级条形图存储所有闪存通道的条纹和分散容量，并映射散射和条纹数据。每个闪存通道都具有一个非易失性存储器件（NVMD），该器件具有将逻辑块地址（LBA）转换为访问NVMD中闪存的物理块地址（PBA）的低级别控制器。磨损平整和坏块重映射由每个NVMD进行。源和阴影闪存块由NVMD回收。两级智能存储交换机支持三级控制器。

73. 发明申请

US20090113121A1 Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes 有权
标题翻译：具有用于组合Flash写入的命令队列的闪存系统中可部署的部分映射表集
公开(公告)号：US20090113121A1
公开(公告)日：2009-04-30
申请号：US12347306
申请日：2008-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G11C16/102 , G11C2216/30
摘要： A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.
摘要翻译：闪存控制器具有访问多电平单元（MLC）闪存的物理块的闪存接口。扩展通用串行总线（EUSB）接口将主机命令加载到命令队列中，其中写入被重新排序并组合以减少闪存写入。 RAM中的部分逻辑到物理L2P映射表仅具有N组L2P映射表中的1个的条目。其他N-1组存储在闪存中，并在发生L2P表错误时被提取到RAM中。映射所需的RAM大大降低。数据缓冲器存储一页主机写入数据。扇区写入使用数据缓冲区进行合并。当写入不同的页面时，数据缓冲区被刷新闪存，而当L2P表错过发生时，部分逻辑到物理映射表被刷新为闪存，当主机地址是N组的L2P中的不同的一个映射表。

74. 发明授权

US08266367B2 Multi-level striping and truncation channel-equalization for flash-memory system 有权
标题翻译：闪存系统的多级条带化和截断通道均衡
公开(公告)号：US08266367B2
公开(公告)日：2012-09-11
申请号：US12475457
申请日：2009-05-29
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma , Myeongjin Shin
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/0631 , G06F3/0688 , G06F2212/7203 , G06F2212/7208 , G11C11/5678 , G11C13/0004 , G11C29/765
摘要： Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.
摘要翻译：截断将所有闪存通道的可用条带数据容量减小到最小闪存通道的容量。固态磁盘（SSD）具有智能存储交换机，通过截断来保护从条带数据容量中移除的闪存存储。超出条带数据容量的额外存储被访问为不带条纹的分散数据。随着更多的坏块出现，条带数据容量的大小随着时间的推移而减少。一级条形图存储所有闪存通道的条纹和分散容量，并映射散射和条纹数据。每个闪存通道都具有一个非易失性存储器件（NVMD），该器件具有将逻辑块地址（LBA）转换为访问NVMD中闪存的物理块地址（PBA）的低级别控制器。磨损平整和坏块重映射由每个NVMD进行。源和阴影闪存块由NVMD回收。两级智能存储交换机支持三级控制器。

75. 发明授权

US08037234B2 Command queuing smart storage transfer manager for striping data to raw-NAND flash modules 有权
标题翻译：命令排队智能存储传输管理器，用于将数据分配到原始NAND闪存模块
公开(公告)号：US08037234B2
公开(公告)日：2011-10-11
申请号：US12252155
申请日：2008-10-15
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F3/0607 , G06F3/0632 , G06F12/0607 , G06F2212/1036 , G06F2212/7203 , G06F2212/7208 , G11C13/0004
摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
摘要翻译：闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。剩余部分指向SDRAM中主机数据的位置。命令队列存储主机命令的Q，R。

76. 发明申请

US20110066837A1 Single-Chip Flash Device with Boot Code Transfer Capability 有权
标题翻译：具有启动代码传输能力的单芯片闪存设备
公开(公告)号：US20110066837A1
公开(公告)日：2011-03-17
申请号：US12947211
申请日：2010-11-16
申请人： Charles C. Lee , Abraham C. Ma , Frank Yu , Shimon Chen
发明人： Charles C. Lee , Abraham C. Ma , Frank Yu , Shimon Chen
IPC分类号： G06F15/177 , G06F12/02 , G06F13/28 , G06F9/24
CPC分类号： G06F9/4401 , G06F13/387 , G06F2213/3854
摘要： A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.
摘要翻译：多媒体卡（MMC）单片闪存器件（SCFD）包含一个MMC闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。这些页面被小RAM缓冲并写入较大的DRAM。一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。引导代码和控制代码在代码更新操作期间被有选择地覆盖以消除存货问题。

77. 发明申请

US20110016267A1 Low-Power USB Flash Card Reader Using Bulk-Pipe Streaming with UAS Command Re-Ordering and Channel Separation 失效
标题翻译：低功耗USB闪存读卡器，使用大容量管道流与UAS命令重新排序和通道分离
公开(公告)号：US20110016267A1
公开(公告)日：2011-01-20
申请号：US12887477
申请日：2010-09-21
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/08 , G06F13/28
CPC分类号： G06F13/28 , G11C13/0004 , G11C16/102 , G11C2216/30 , Y02D10/14
摘要： A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.
摘要翻译：闪存卡读卡器通过使用多个管道的批量流传输来提高传输效率。批量数据输出管道将主机写入数据传送到读卡器，并且可以与承载从附接到读卡器的闪存卡读取的主机读取数据的批量数据输入管并行操作。状态数据包不会阻塞数据包，因为状态数据包通过单独的状态管道进行缓冲，命令通过命令管道缓冲。来自多个闪存卡的闪存数据被交织为共享大容量数据管道的单独端点。数据输入/输出流状态机通过批量数据输入和数据输出管道控制流批量数据，而状态流状态机通过状态管道控制流状态数据包。使用批量流量减少事务开销，其中几个命令的数据包被组合成相同的批量流。

78. 发明申请

US20100275037A1 Low-Power USB SuperSpeed Device with 8-bit Payload and 9-bit Frame NRZI Encoding for Replacing 8/10-bit Encoding 失效
标题翻译：具有8位有效载荷和9位帧NRZI编码的低功耗USB超速设备，用于替换8/10位编码
公开(公告)号：US20100275037A1
公开(公告)日：2010-10-28
申请号：US12831160
申请日：2010-07-06
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma , Jim Chin-Nan Ni , Shimon Chen
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma , Jim Chin-Nan Ni , Shimon Chen
IPC分类号： G06F13/36 , G06F13/10 , G06F1/04 , G06F13/28 , H04L9/00 , G06F1/32
CPC分类号： G06F13/385 , G11C16/102 , G11C2216/30 , Y02D10/14 , Y02D10/151
摘要： A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.
摘要翻译：低功耗闪存设备使用修改后的通用串行总线（USB）3.0协议来降低功耗。当应用程序中的USB电缆长度短时，位时钟减慢了功率，并且需要预加重。通过消除8/10位编码器并将同步和成帧字节编码为9位符号来提高数据效率。数据字节只有在数据中出现一系列6个数据字节时才能通过位填充进行扩展。标头和有效载荷数据以每个数据字节近8位的形式传输，而成帧是每个符号9位，远远小于每个字节的标准10位。使用低功率链路层，物理层和缩小协议层。读卡器转换器集线器允许USB主机访问低功耗USB设备。只有一个闪存设备被访问，与标准的USB广播相比，将功耗降低到多个设备。

79. 发明授权

US07809862B2 Dual-mode switch for multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage 有权
标题翻译：用于多媒体卡/安全数字（MMC / SD）控制器的双模式开关从集成闪存读取上电启动代码，用于用户存储
公开(公告)号：US07809862B2
公开(公告)日：2010-10-05
申请号：US12426189
申请日：2009-04-17
申请人： I-Kang Frank Yu , Abraham C. Ma , Charles C. Lee
发明人： I-Kang Frank Yu , Abraham C. Ma , Charles C. Lee
IPC分类号： G06F3/00 , G06F13/36
CPC分类号： G06F13/28 , Y02D10/14
摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.
摘要翻译：多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含MMC / SD闪存微控制器和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是可随机寻址的闪存阵列。来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

80. 发明申请

US20090204872A1 Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules 审中-公开
公开(公告)号：US20090204872A1
公开(公告)日：2009-08-13
申请号：US12427675
申请日：2009-04-21
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma
IPC分类号： G06F12/08 , G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0616 , G06F3/0659 , G06F3/0685 , G06F3/0688 , G06F12/0607 , G06F12/0804 , G06F2212/7201 , G06F2212/7203 , G06F2212/7208 , G11C7/00 , G11C11/5621 , G11C11/5678 , G11C13/0004 , G11C16/0483
摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

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