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    • 71. 发明申请
    • MEMORY CACHE SHARING IN HYBRID HARD DISK
    • 混合硬盘中的内存缓存共享
    • US20090089500A1
    • 2009-04-02
    • US11864791
    • 2007-09-28
    • Yong Jiang
    • Yong Jiang
    • G06F12/06G06F12/00
    • G06F12/0873G06F2212/222G06F2212/284G06F2212/313
    • A system allows one or more hybrid hard disks or any other storage devices to share a logical nonvolatile device formed by one or more non-volatile memory devices. The system comprises a control logic to reserve on a hybrid hard disk a space that corresponds to a non-volatile memory device in the hybrid hard disk and to use a space access instruction to access the non-volatile memory device. The control logic accesses the logical non-volatile memory device in an event that a content of a storage device is stored in the logical non-volatile memory device in response to an instruction to access the storage device.
    • 系统允许一个或多个混合硬盘或任何其他存储设备共享由一个或多个非易失性存储器设备形成的逻辑非易失性设备。 该系统包括控制逻辑,以在混合硬盘上预留对应于混合硬盘中的非易失性存储器设备的空间,并且使用空间访问指令来访问非易失性存储器设备。 在存储装置的内容响应于访问存储装置的指令而存储在逻辑非易失性存储装置中的情况下,控制逻辑访问逻辑非易失性存储装置。
    • 73. 发明授权
    • Network interface with double date rate and delay locked loop
    • 具有双倍日期速率和延迟锁定环路的网络接口
    • US07308568B2
    • 2007-12-11
    • US11580956
    • 2006-10-16
    • Jonathan LinYong Jiang
    • Jonathan LinYong Jiang
    • G03F7/38
    • G06F13/385H03L7/0812H04J3/0697H04L49/351H04L49/352H04L49/354H04L49/40
    • A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port. The external clock signal is input to the programmable delay locked loop, which outputs an output clock signal having a frequency equal to the frequency of the external clock signal, in synchronization with the data being output.
    • 提供一种网络设备,其包括设备输入,至少一个端口,倍频器,数据I / O设备和可编程延迟锁定环路。 倍频器耦合到输入并被配置为接收输入信号并输出​​具有输入信号频率的两倍的输出信号。 数据I / O设备被配置为基于参考时钟信号输出数据。 可编程延迟锁定环路耦合到设备输入端并被配置为接收输入信号并自动输出来自输入信号的异相预定量的输出信号。 在器件输入端接收的外部时钟信号输入倍频器。 倍频器的输出作为参考时钟输入到数据I / O设备。 数据(例如,从内部设备逻辑)从数据I / O设备输出到至少一个端口。 外部时钟信号被输入到可编程延迟锁定环路,与输出的数据同步地输出具有等于外部时钟信号频率的频率的输出时钟信号。
    • 74. 发明授权
    • Network interface with double data rate and delay locked loop
    • 具有双数据速率和延迟锁定环路的网络接口
    • US06920552B2
    • 2005-07-19
    • US10083291
    • 2002-02-27
    • Jonathan LinYong Jiang
    • Jonathan LinYong Jiang
    • H03L7/081H04J3/06H04L12/56G03F7/38
    • G06F13/385H03L7/0812H04J3/0697H04L49/351H04L49/352H04L49/354H04L49/40
    • A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port. The external clock signal is input to the programmable delay locked loop, which outputs an output clock signal having a frequency equal to the frequency of the external clock signal, in synchronization with the data being output.
    • 提供一种网络设备,其包括设备输入,至少一个端口,倍频器,数据I / O设备和可编程延迟锁定环路。 倍频器耦合到输入并被配置为接收输入信号并输出​​具有输入信号频率的两倍的输出信号。 数据I / O设备被配置为基于参考时钟信号输出数据。 可编程延迟锁定环路耦合到设备输入端并被配置为接收输入信号并自动输出来自输入信号的异相预定量的输出信号。 在器件输入端接收的外部时钟信号输入倍频器。 倍频器的输出作为参考时钟输入到数据I / O设备。 数据(例如,从内部设备逻辑)从数据I / O设备输出到至少一个端口。 外部时钟信号被输入到可编程延迟锁定环路,与输出的数据同步地输出具有等于外部时钟信号频率的频率的输出时钟信号。
    • 75. 发明申请
    • Mist iron
    • 薄雾铁
    • US20050069302A1
    • 2005-03-31
    • US10498770
    • 2002-12-03
    • Nyik WongYong JiangTao GuoKumar Asok S/O Kasevan
    • Nyik WongYong JiangTao GuoKumar Asok S/O Kasevan
    • D06F75/10D06F75/22F22B1/30
    • D06F75/22D06F75/10
    • An iron comprising a housing (1), a heatable soleplate (4) and means for generating very fine liquid droplets to be expelled from at least one discharge opening (9) of the iron, said means comprising at least one air passage (8) for pressurized air supply and at least one liquid passage (13) for pressurized liquid supply, said air passage (8) and said liquid passage (13) communicating with each other for mixing air and liquid, said mixture of air and liquid being supplied to the discharge opening (9). To improve the generation of fine liquid droplets (mist) an outlet of the liquid passage (8) ends into the air passage (13) upstream of the discharge opening (9) to introduce liquid into the air passage and an outlet of the air passage is provided with a nozzle (10) having said discharge opening (9). Preferably the pressurized air and liquid supply is obtained by means of electric pumps (6,7). The liquid may be water or a (diluted) additive liquid.
    • 一种熨斗,包括壳体(1),可加热底板(4)和用于产生要从铁的至少一个排放开口(9)排出的非常细的液滴的装置,所述装置包括至少一个空气通道(8) 用于加压空气供应和用于加压液体供应的至少一个液体通道(13),所述空气通道(8)和所述液体通道(13)彼此连通以混合空气和液体,所述空气和液体混合物供应到 排出口(9)。 为了改善细液滴(雾)的产生,液体通道(8)的出口在排出口(9)的上游端部进入空气通道(13),以将液体引入空气通道和空气通道的出口 设置有具有所述排出口(9)的喷嘴(10)。 优选地,加压空气和液体供应通过电动泵(6,7)获得。 液体可以是水或(稀释的)添加剂液体。
    • 77. 发明授权
    • System and method for a flexible memory controller
    • 灵活的内存控制器的系统和方法
    • US5933385A
    • 1999-08-03
    • US903720
    • 1997-07-31
    • Yong JiangPing Lo
    • Yong JiangPing Lo
    • G11C7/10G11C7/22G11C7/00
    • G11C7/22G11C7/1072
    • A flexible memory controller capable of performing any combination of read, write and deselect operations is described. The present invention can store two pending write or read operations and perform a third write or read operation. In a ZBT SRAM embodiment the memory controller has three address registers, two data registers, and two comparators. Addresses for pending memory access operations are shifted in the address registers so that memory access addresses can be stored without overwriting the memory addresses for the pending operations. Similarly, data is shifted in the data registers to ensure that data remains available for pending memory access operations. The specific register operations are controlled by a thirteen state state machine. The thirteen states and the relationships between the states are defined to enable the memory controller to perform any combination of read, write and deselect operations without inserting idle cycles. When a read address matches the address of a pending write operation it indicates that the data that the read address is intended to retrieve has not yet been written to the memory array. The data for this read operation may be in one or more places including the memory I/O pins, either of the two data registers, or inside the memory. The state machine includes a series of logical comparisons to identify the location of the desired data. After the data location is determined the data is loaded into the output register.
    • 描述能够执行读取,写入和取消选择操作的任何组合的灵活的存储器控​​制器。 本发明可以存储两个待处理的写入或读取操作并执行第三次写入或读取操作。 在ZBT SRAM实施例中,存储器控制器具有三个地址寄存器,两个数据寄存器和两个比较器。 待处理的存储器访问操作的地址在地址寄存器中被移位,使得可以存储存储器访问地址而不覆盖待处理操作的存储器地址。 类似地,数据在数据寄存器中移位,以确保数据保持可用于待机内存访问操作。 特定的寄存器操作由十三个状态机控制。 定义了十三个状态和状态之间的关系,以使内存控制器能够执行读取,写入和取消选择操作的任何组合,而不会插入空闲周期。 当读取地址与待处理写入操作的地址匹配时,它指示读取地址要检索的数据尚未写入存储器阵列。 该读取操作的数据可以在一个或多个位置,包括存储器I / O引脚,两个数据寄存器中的任一个或存储器内。 状态机包括一系列逻辑比较,以识别所需数据的位置。 确定数据位置后,将数据加载到输出寄存器中。