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71. 发明申请

US20060044893A1 Non-volatile one time programmable memory 有权
公开(公告)号：US20060044893A1
公开(公告)日：2006-03-02
申请号：US10933205
申请日：2004-09-02
申请人： Benjamin Louie , Ebrahim Abedifard
发明人： Benjamin Louie , Ebrahim Abedifard
IPC分类号： G11C7/00
CPC分类号： G11C16/22 , G11C16/3436
摘要： A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in the block is programmed. Once that page/bit is programmed, the one time programmable memory block is locked against further programming or erasing.

72. 发明授权

US08291272B2 Macro and command execution from memory array 有权
标题翻译：宏和命令从内存数组执行
公开(公告)号：US08291272B2
公开(公告)日：2012-10-16
申请号：US13346290
申请日：2012-01-09
申请人： Frankie F. Roohparvar , Benjamin Louie
发明人： Frankie F. Roohparvar , Benjamin Louie
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C16/04
摘要： Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation.
摘要翻译：公开了利用存储在存储器件的存储器阵列中的指令执行存储器件的内部操作的方法和装置。还公开了适于解释存储在存储器件中的指令和数据的解码块。通过执行存储在执行自检操作的存储器件的存储器阵列中的测试程序，可以使用方法来执行存储器件的内部自检操作。

73. 发明授权

US07962784B2 Repairable block redundancy scheme 有权
标题翻译：可修复块冗余方案
公开(公告)号：US07962784B2
公开(公告)日：2011-06-14
申请号：US12427461
申请日：2009-04-21
申请人： Vinod Lakhani , Benjamin Louie
发明人： Vinod Lakhani , Benjamin Louie
IPC分类号： G06F11/00
CPC分类号： G11C29/808 , G11C29/76
摘要： A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses.
摘要翻译：公开了一种用于闪速存储器件内的块替换的方案，其使用可编程查找表来存储当接收到某些输入块地址时用于块选择的新地址。每当在输入地址中检测到地址转换时，新的地址被加载到可编程熔丝锁存器中。新地址可能包含块地址或块和银行地址。

74. 发明授权

US07852681B2 Non-volatile one time programmable memory 有权
标题翻译：非易失性一次可编程存储器
公开(公告)号：US07852681B2
公开(公告)日：2010-12-14
申请号：US12426689
申请日：2009-04-20
申请人： Benjamin Louie , Ebrahim Abedifard
发明人： Benjamin Louie , Ebrahim Abedifard
IPC分类号： G11C11/34
CPC分类号： G11C16/22 , G11C16/3436
摘要： A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in the block is programmed. Once that page/bit is programmed, the one time programmable memory block is locked against further programming or erasing.
摘要翻译：在一次性可编程存储器块上执行验证操作，以确定其是否已被编程。如果任何位被编程，则进一步编程或擦除被禁止。在另一个实施例中，可以编程和擦除存储器块，直到块中的预定页面或锁定位被编程为止。一旦该页/位被编程，一次可编程存储块被锁定以进一步编程或擦除。

75. 发明申请

US20090207665A1 NON-VOLATILE ONE TIME PROGRAMMABLE MEMORY 有权
标题翻译：非易失性一次性可编程存储器
公开(公告)号：US20090207665A1
公开(公告)日：2009-08-20
申请号：US12426689
申请日：2009-04-20
申请人： Benjamin Louie , Ebrahim Abedifard
发明人： Benjamin Louie , Ebrahim Abedifard
IPC分类号： G11C16/06 , G11C7/00 , G11C8/00
CPC分类号： G11C16/22 , G11C16/3436
摘要： A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in the block is programmed. Once that page/bit is programmed, the one time programmable memory block is locked against further programming or erasing.
摘要翻译：在一次性可编程存储器块上执行验证操作，以确定其是否已被编程。如果任何位被编程，则进一步编程或擦除被禁止。在另一个实施例中，可以编程和擦除存储器块，直到块中的预定页面或锁定位被编程为止。一旦该页/位被编程，一次可编程存储块被锁定以进一步编程或擦除。

76. 发明申请

US20090113262A1 SYSTEM AND METHOD FOR CONDITIONING AND IDENTIFYING BAD BLOCKS IN INTEGRATED CIRCUITS 审中-公开
标题翻译：在集成电路中调节和识别边缘块的系统和方法
公开(公告)号：US20090113262A1
公开(公告)日：2009-04-30
申请号：US11862894
申请日：2007-09-27
申请人： Brandon Lee Fernandes , Benjamin Louie
发明人： Brandon Lee Fernandes , Benjamin Louie
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318536
摘要： An electronic system of an Integrated circuit (IC) for conditioning and identification of bad blocks in the IC is disclosed. The electronic system includes at least one cyclic scan chain and at least one multiplexer. A cyclic scan chain includes a plurality of flip-flops, which are connected in a cascaded manner. A multiplexer is connected between two adjacent flip-flops of the cyclic shift register. The multiplexer has a first input pin connected to output of a first flip-flop, a second input pin connected to a user pin and an output pin connected to an input of a second flip-flop. The multiplexer is configured to condition the plurality of flip-flops through the user pin by programming logic bits in the plurality of flip-flop. The output of the first flip-flop is configured to read the logic bits in the plurality of flip-flops to identify a bad block in the IC.
摘要翻译：公开了一种用于调节和识别IC中坏块的集成电路（IC）的电子系统。电子系统包括至少一个循环扫描链和至少一个多路复用器。循环扫描链包括以级联方式连接的多个触发器。多路复用器连接在循环移位寄存器的两个相邻的触发器之间。多路复用器具有连接到第一触发器的输出的第一输入引脚，连接到用户引脚的第二输入引脚和连接到第二触发器的输入的输出引脚。复用器被配置为通过编程多个触发器中的逻辑位来通过用户引脚来调节多个触发器。第一触发器的输出被配置为读取多个触发器中的逻辑位以识别IC中的坏块。

77. 发明申请

US20080209284A1 Input/output compression and pin reduction in an integrated circuit 有权
标题翻译：集成电路中的输入/输出压缩和引脚降低
公开(公告)号：US20080209284A1
公开(公告)日：2008-08-28
申请号：US11709982
申请日：2007-02-23
申请人： Benjamin Louie , Scott N. Gatzemeier , Adam Johnson , Frankie F. Roohparvar
发明人： Benjamin Louie , Scott N. Gatzemeier , Adam Johnson , Frankie F. Roohparvar
IPC分类号： G11C29/00
CPC分类号： G01R31/318547 , G11C29/1201 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test data from the memory array/logic circuit. An I/O scan register is coupled to each I/O pad for converting serial data to parallel and parallel data to serial in response to a test mode select signal, a test data input, and a test clock.
摘要翻译：用于测试存储器阵列和/或逻辑电路的I / O压缩装置包括从存储器阵列/逻辑电路输出压缩测试数据的可选压缩电路。 I / O扫描寄存器耦合到每个I / O焊盘，用于响应于测试模式选择信号，测试数据输入和测试时钟将串行数据转换为并行数据到并行数据。

78. 发明申请

US20070074070A1 Repairable block redundancy scheme 有权
公开(公告)号：US20070074070A1
公开(公告)日：2007-03-29
申请号：US11604744
申请日：2006-11-28
申请人： Vinod Lakhani , Benjamin Louie
发明人： Vinod Lakhani , Benjamin Louie
IPC分类号： G06F11/00
CPC分类号： G11C29/808 , G11C29/76
摘要： A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when certain input block addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in the input address. The new addresses may contain block addresses or block and bank addresses.

79. 发明申请

US20070064497A1 Non-volatile one time programmable memory 有权
公开(公告)号：US20070064497A1
公开(公告)日：2007-03-22
申请号：US11600356
申请日：2006-11-16
申请人： Benjamin Louie , Ebrahim Abedifard
发明人： Benjamin Louie , Ebrahim Abedifard
IPC分类号： G11C16/04
CPC分类号： G11C16/22 , G11C16/3436
摘要： A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further programming or erasing is inhibited. In another embodiment, the memory block can be programmed and erased until a predetermined page or lock bit in the block is programmed. Once that page/bit is programmed, the one time programmable memory block is locked against further programming or erasing.

80. 发明授权

US07154782B2 Contiguous block addressing scheme 有权
公开(公告)号：US07154782B2
公开(公告)日：2006-12-26
申请号：US11207105
申请日：2005-08-18
申请人： Vinod Lakhani , Benjamin Louie
发明人： Vinod Lakhani , Benjamin Louie
IPC分类号： G11C11/00
CPC分类号： G06F12/0246 , G11C16/04 , G11C29/76 , G11C29/808 , G11C29/82
摘要： An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement.

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