专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20140027901A1 PACKAGE-ON-PACKAGE STRUCTURES HAVING BUFFER DAMS AND METHODS FOR FORMING THE SAME 有权
标题翻译：具有缓冲器数据包的封装结构及其形成方法
公开(公告)号：US20140027901A1
公开(公告)日：2014-01-30
申请号：US13559153
申请日：2012-07-26
申请人： Yen-Chang Hu , Ching-Wen Hsiao , Chen-Shien Chen
发明人： Yen-Chang Hu , Ching-Wen Hsiao , Chen-Shien Chen
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L21/566 , H01L21/02288 , H01L21/02356 , H01L21/568 , H01L21/6835 , H01L23/3121 , H01L24/19 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/04105 , H01L2224/32245 , H01L2224/73267 , H01L2225/06524 , H01L2225/06548 , H01L2225/06589 , H01L2225/06593 , H01L2225/1035 , H01L2924/181 , H01L2924/00
摘要： A device includes a device die and a plurality of metal posts at a surface of the device die and electrically coupled to the device die. The device further includes a plurality of through-assembly vias (TAVs), a dam member between the device die and the plurality of TAVs, and a polymer layer encompassing the device die, the plurality of metal posts, the plurality of TAVs, and the dam member.
摘要翻译：一种器件包括器件裸片和在器件裸片的表面处的多个金属柱，并且电耦合到器件裸片。该装置还包括多个通过组装通孔（TAV），在器件管芯和多个TAV之间的阻挡构件，以及包围器件管芯，多个金属管柱，多个TAV以及水坝成员

72. 发明授权

US08624360B2 Cooling channels in 3DIC stacks 有权
标题翻译： 3DIC堆栈中的冷却通道
公开(公告)号：US08624360B2
公开(公告)日：2014-01-07
申请号：US12616562
申请日：2009-11-11
申请人： Kai-Ming Ching , Ching-Wen Hsiao , Tsung-Ding Wang , Ming-Hong Tseng , Chen-Shien Chen
发明人： Kai-Ming Ching , Ching-Wen Hsiao , Tsung-Ding Wang , Ming-Hong Tseng , Chen-Shien Chen
IPC分类号： H01L29/40 , H01L23/02 , H01L23/34 , H01L23/48 , H01L23/52
CPC分类号： H01L25/0657 , H01L23/46 , H01L23/473 , H01L23/481 , H01L23/49811 , H01L23/49827 , H01L23/49894 , H01L23/5226 , H01L24/82 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/13147 , H01L2225/06513 , H01L2225/06527 , H01L2225/06544 , H01L2225/06589 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.
摘要翻译：集成电路结构包括：具有半导体衬底的裸片; 半导体衬底上的电介质层; 包括电介质层中的金属线和通孔的互连结构; 从所述半导体衬底的内部延伸到所述电介质层的内部的多个沟道; 以及在所述多个通道的互连结构和密封部分上的电介质膜。多个通道被配置成允许流体流过。

73. 发明申请

US20130182402A1 PoP Structures Including Through-Assembly Via Modules 有权
标题翻译： PoP结构包括通过模块的通过组件
公开(公告)号：US20130182402A1
公开(公告)日：2013-07-18
申请号：US13352937
申请日：2012-01-18
申请人： Chih-Hua Chen , Chen-Shien Chen , Ching-Wen Hsiao
发明人： Chih-Hua Chen , Chen-Shien Chen , Ching-Wen Hsiao
IPC分类号： H05K7/04
CPC分类号： H05K7/1061 , H01L21/568 , H01L21/6835 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5389 , H01L24/19 , H01L25/0657 , H01L25/105 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68381 , H01L2224/12105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/9202 , H01L2224/9222 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/00
摘要： A device includes a Through-Assembly Via (TAV) Module, which includes a substrate, a plurality of through-vias penetrating through the substrate, and a second plurality of metal posts at a bottom surface of the TAV module and electrically coupled to the plurality of through-vias. A polymer includes a first portion between and contacting sidewalls of the first package component and the TAV module, a second portion disposed between the first plurality of metal posts, and a third portion disposed between the second plurality of metal posts. A first plurality of Redistribution Lines (RDLs) is underlying a bottom surface of the second and the third portions of the polymer. A second plurality of RDLs is over the first package component and the TAV module. The first plurality of RDLs is electrically coupled to the second plurality of RDLs through the plurality of through-vias in the TAV module.
摘要翻译：一种装置包括一个直通组件通孔（TAV）模块，该组件通孔（TAV）模块包括一个衬底，穿过该衬底的多个贯通孔，以及在该TAV模块的底部表面上的第二个多个金属柱，的通孔。聚合物包括在第一包装部件和TAV模块之间和接触侧壁之间的第一部分和设置在第一多个金属柱之间的第二部分和设置在第二多个金属柱之间的第三部分。第一多个再分配线（RDL）位于聚合物的第二和第三部分的底表面下方。第二组多个RDL在第一封装组件和TAV模块之上。第一组多个RDL通过TAV模块中的多个通孔电耦合到第二多个RDL。

74. 发明申请

US20130181325A1 Through-Assembly Via Modules and Methods for Forming the Same 有权
公开(公告)号：US20130181325A1
公开(公告)日：2013-07-18
申请号：US13352093
申请日：2012-01-17
申请人： Chih-Hua Chen , Chen-Shien Chen , Ching-Wen Hsiao
发明人： Chih-Hua Chen , Chen-Shien Chen , Ching-Wen Hsiao
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L21/7687 , H01L21/486 , H01L21/76898 , H01L21/78 , H01L23/147 , H01L23/15 , H01L23/481 , H01L23/49827 , H01L2224/06181 , H01L2924/0002 , H01L2924/00
摘要： A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.

75. 发明授权

US08318596B2 Pillar structure having a non-planar surface for semiconductor devices 有权
标题翻译：具有用于半导体器件的非平面表面的柱结构
公开(公告)号：US08318596B2
公开(公告)日：2012-11-27
申请号：US12704183
申请日：2010-02-11
申请人： Tin-Hao Kuo , Chen-Shien Chen , Ching-Wen Hsiao
发明人： Tin-Hao Kuo , Chen-Shien Chen , Ching-Wen Hsiao
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/13016 , H01L2224/13018 , H01L2224/13022 , H01L2224/13076 , H01L2224/1308 , H01L2224/13084 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/16507 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.
摘要翻译：提供了一种用于半导体器件的导电柱。导电柱形成为使得顶表面是非平坦的。在实施例中，顶表面可以是凹形，凸形或波浪状。可以在导电柱上形成可选的覆盖层，以允许更强的金属间化合物（IMC）层。 IMC层是在焊料材料和下层之间形成的层，例如导电柱或可选的封盖层。

76. 发明申请

US20110227216A1 Under-Bump Metallization Structure for Semiconductor Devices 审中-公开
标题翻译：半导体器件欠冲击金属化结构
公开(公告)号：US20110227216A1
公开(公告)日：2011-09-22
申请号：US12725322
申请日：2010-03-16
申请人： Ming-Hung Tseng , Chen-Shien Chen , Chen-Cheng Kuo , Chih-Hua Chen , Ching-Wen Hsiao
发明人： Ming-Hung Tseng , Chen-Shien Chen , Chen-Cheng Kuo , Chih-Hua Chen , Ching-Wen Hsiao
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/11 , H01L24/05 , H01L24/13 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05083 , H01L2224/05184 , H01L2224/05541 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/45144 , H01L2224/48624 , H01L2224/48639 , H01L2224/48647 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2224/05005
摘要： An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer.
摘要翻译：提供了一种用于半导体器件的凸块下金属化（UBM）结构。钝化层形成在接触焊盘上，使得接触焊盘的至少一部分被暴露。可以在钝化层上方形成保护层，例如聚酰亚胺层。诸如导电柱的UBM结构形成在下面的接触焊盘之上，使得下面的接触焊盘横向延伸越过UBM结构一个足够大的距离，以防止或减少钝化层和/或保护层的破裂。

77. 发明申请

US20110193227A1 Methods and Apparatus for Robust Flip Chip Interconnections 有权
标题翻译：用于鲁棒倒装芯片互连的方法和装置
公开(公告)号：US20110193227A1
公开(公告)日：2011-08-11
申请号：US12729021
申请日：2010-03-22
申请人： Yao-Chun Chuang , Ching-Wen Hsiao , Chen-Cheng Kuo , Chen-Shien Chen
发明人： Yao-Chun Chuang , Ching-Wen Hsiao , Chen-Cheng Kuo , Chen-Shien Chen
IPC分类号： H01L23/488 , H01L21/60 , H01L23/31
CPC分类号： H01L23/49816 , H01L23/49811 , H01L23/49866 , H01L24/13 , H01L24/16 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/13169 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/01027 , H01L2924/01083 , H01L2924/01015 , H01L2224/13099 , H01L2924/00
摘要： Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %.
摘要翻译：公开了使用无铅焊料在倒装芯片布置中提供坚固的焊接连接的装置和方法。铜列从集成电路的输入/输出端子延伸。包含镍，镍合金，钯，铂，钴，银，金及其合金的材料的盖层形成在铜柱的外表面上。无铅焊料连接器设置在盖层上。具有金属整理剂焊盘的基板与焊料连接器对准。进行热回流。金属表面可以是镍，镍合金和镍基材料。在热回流之后，形成在铜端子柱和金属表面焊料焊盘之间的焊接连接小于0.5wt。％。

78. 发明授权

US07929564B2 System, apparatus, and method for loading bits into sub-channels 有权
标题翻译：用于将比特加载到子信道中的系统，装置和方法
公开(公告)号：US07929564B2
公开(公告)日：2011-04-19
申请号：US12048339
申请日：2008-03-14
申请人： Ta-Sung Lee , Ching-Wen Hsiao
发明人： Ta-Sung Lee , Ching-Wen Hsiao
IPC分类号： H04J3/16
CPC分类号： H04L5/0046 , H04L5/006
摘要： An apparatus and a method for loading a predetermined number of bits into a plurality of sub-channels are provided. The apparatus comprises a sort module, a calculation module, and a decision module. The sort module is configured to sort the sub-channels into a plurality of sorted sub-channels according to the quality value of each of the sub-channels. The calculation module is configured to calculate the difference value for each of the sorted sub-channels, except for the first sorted sub-channel, according to the corresponding quality value. The decision module is configured to decide a number of bits for each of the sorted sub-channels according to the difference values, wherein a summation of the numbers is equal to the predetermined number. The apparatus and the method are able to load bits efficiently according to the difference values.
摘要翻译：提供了一种用于将预定数量的位加载到多个子信道中的装置和方法。该装置包括分类模块，计算模块和决策模块。分类模块被配置为根据每个子信道的质量值将子信道分类为多个排序子信道。计算模块被配置为根据相应的质量值来计算除了第一排序子信道之外的每个排序子信道的差值。决定模块被配置为根据差值来确定每个排序子信道的比特数，其中数字的求和等于预定数量。该装置和方法能够根据差值有效地加载比特。

79. 发明申请

US20110068465A1 STRONG INTERCONNECTION POST GEOMETRY 有权
标题翻译：强大的互连后几何
公开(公告)号：US20110068465A1
公开(公告)日：2011-03-24
申请号：US12623925
申请日：2009-11-23
申请人： Wen-Wei Shen , Chen-Shien Chen , Chen-Cheng Kuo , Chih-Hua Chen , Ching-Wen Hsiao
发明人： Wen-Wei Shen , Chen-Shien Chen , Chen-Cheng Kuo , Chih-Hua Chen , Ching-Wen Hsiao
IPC分类号： H01L23/488
CPC分类号： H01L24/16 , H01L24/13 , H01L24/81 , H01L2224/13005 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16 , H01L2224/16237 , H01L2224/81191 , H01L2224/812 , H01L2224/814 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/10329 , H01L2924/10336 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/381 , H01L2924/00014 , H01L2924/01083 , H01L2224/13099 , H01L2924/00 , H01L2924/206 , H01L2924/207
摘要： A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch.
摘要翻译：公开了一种倒装芯片封装组件和集成电路器件。示例性的倒装芯片封装组件包括第一基板; 第二基板; 以及设置在第一基板和第二基板之间的接合结构。每个接头结构包括在第一基板和第二基板之间的互连柱和在互连柱和第二基板之间的接合焊料，其中互连柱呈现宽度和第一高度。间距定义每个关节结构之间的距离。第一高度小于音高的一半。

80. 发明申请

US20090232156A1 System, Apparatus, and Method for Loading Bits into Sub-Channels 有权
标题翻译：用于将位加载到子通道中的系统，设备和方法
公开(公告)号：US20090232156A1
公开(公告)日：2009-09-17
申请号：US12048339
申请日：2008-03-14
申请人： Ta-Sung Lee , Ching-Wen Hsiao
发明人： Ta-Sung Lee , Ching-Wen Hsiao
IPC分类号： H04J15/00
CPC分类号： H04L5/0046 , H04L5/006
摘要： An apparatus and a method for loading a predetermined number of bits into a plurality of sub-channels are provided. The apparatus comprises a sort module, a calculation module, and a decision module. The sort module is configured to sort the sub-channels into a plurality of sorted sub-channels according to the quality value of each of the sub-channels. The calculation module is configured to calculate the difference value for each of the sorted sub-channels, except for the first sorted sub-channels, according to the corresponding quality value. The decision module is configured to decide a number of bits for each of the sorted sub-channels according to the difference values, wherein a summation of the numbers is equal to the predetermined number. The apparatus and the method are able to load bits efficiently according to the difference values.
摘要翻译：提供了一种用于将预定数量的比特加载到多个子信道中的装置和方法。该装置包括分类模块，计算模块和决策模块。分类模块被配置为根据每个子信道的质量值将子信道分类为多个排序子信道。计算模块被配置为根据相应的质量值来计算除了第一排序子信道之外的每个排序子信道的差值。决定模块被配置为根据差值来确定每个排序子信道的比特数，其中数字的和等于预定数。该装置和方法能够根据差值有效地加载比特。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式