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71. 发明授权

US06476666B1 Bootstrapped charge pump 失效
标题翻译：自举电荷泵
公开(公告)号：US06476666B1
公开(公告)日：2002-11-05
申请号：US09873017
申请日：2001-05-30
申请人： Chaitanya Palusa , Abhijit Ray
发明人： Chaitanya Palusa , Abhijit Ray
IPC分类号： G05F302
CPC分类号： H02M3/073 , H02M2003/077
摘要： The diode drops associated with the output voltage from a conventional charge pump are eliminated in the present invention with a dual-chain charge pump that utilizes the pumped voltages from each charge pump chain to drive the gates of the other charge pump chain. As a result, the voltages on the gates of the transistors are pumped up to a level such that there is no threshold voltage drop across the transistor, and thus, making it behave like an ideal switch.
摘要翻译：在本发明中，与使用来自每个电荷泵链的泵浦电压驱动另一个电荷泵链的栅极的双链电荷泵相反，在常规电荷泵中与二极管相关的输出电压降低。结果，晶体管的栅极上的电压被泵送到一个水平，使得晶体管两端没有阈值电压降，从而使其像理想的开关一样工作。

72. 发明授权

US6097179A Temperature compensating compact voltage regulator for integrated circuit device 有权
标题翻译：用于集成电路器件的温度补偿紧凑型稳压器
公开(公告)号：US6097179A
公开(公告)日：2000-08-01
申请号：US264092
申请日：1999-03-08
申请人： Abhijit Ray , Raghava Madhu
发明人： Abhijit Ray , Raghava Madhu
IPC分类号： G05F3/24 , G05F3/08 , G05F1/10 , H03K17/00
CPC分类号： G05F3/245 , Y10S323/907
摘要： A voltage regulator circuit (100), coupled between a high power supply voltage (VCC) and a lower power supply voltage (VSS), provides a regulated voltage (XDD) that is greater than the high power supply voltage (VCC). The voltage regulator circuit (100) includes a temperature compensating detect circuit (102) which activates a trigger signal when the XDD voltage exceeds a predetermined level. In response to an active trigger signal, a shunt circuit (104) couples the regulated voltage (XDD) to the high power supply voltage (VCC). The regulated voltage (XDD) is translated to the detect circuit (102) by the regulated voltage (XDD) being applied to the gate of a transistor (N112) disposed between the high power supply voltage (VCC) and a detect node (108). This arrangement allows monitoring of the regulated voltage (XDD) level without loading the regulated voltage (XDD).
摘要翻译：耦合在高电源电压（VCC）和较低电源电压（VSS）之间的稳压器电路（100）提供大于高电源电压（VCC）的调节电压（XDD）。电压调节器电路（100）包括温度补偿检测电路（102），其在XDD电压超过预定电平时激活触发信号。响应于有源触发信号，分流电路（104）将调节电压（XDD）耦合到高电源电压（VCC）。调节电压（XDD）被施加到设置在高电源电压（VCC）和检测节点（108）之间的晶体管（N112）的栅极的调节电压（XDD）转换到检测电路（102）。这种布置允许监视调节电压（XDD）电平而不加载调节电压（XDD）。

73. 发明授权

US6016270A Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations 失效
标题翻译：闪存架构利用时间共享地址总线方案和单独的存储单元访问路径，用于同时读/写操作
公开(公告)号：US6016270A
公开(公告)日：2000-01-18
申请号：US36558
申请日：1998-03-06
申请人： Damodar Reddy Thummalapally , Abhijit Ray
发明人： Damodar Reddy Thummalapally , Abhijit Ray
IPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/10 , G11C2216/22
摘要： A flash memory architecture relies on a single, time-shared address bus to enable a read operation to be performed simultaneously with an algorithm operation when the read operation is targeted for a memory cell block that is not currently tagged for an algorithm operation. After a read address has been latched into the array block selected for the read operation, the address bus is "free" for the remainder of the read operation cycle. During this free time, the address bus can be used for algorithm operations to load the counter address into an active tagged block in the array. Separate global data I/O lines are provided to facilitate simultaneous read and algorithm operations.
摘要翻译：闪速存储器架构依赖于单个时间共享的地址总线，以使得当读操作针对当前未被标记用于算法操作的存储器单元块时，可以与算法操作同时执行读操作。在读取地址被锁存到为读操作选择的数组块之后，地址总线在读操作周期的其余部分是“空闲的”。在这个空闲时间期间，地址总线可用于算法操作，以将计数器地址加载到阵列中的活动标记块中。提供单独的全局数据I / O线以便于同时读取和算法操作。

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