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71. 发明申请

US20060115978A1 Charge-trapping memory cell and method for production 有权
标题翻译：电荷俘获记忆体和生产方法
公开(公告)号：US20060115978A1
公开(公告)日：2006-06-01
申请号：US11000350
申请日：2004-11-30
申请人： Michael Specht , Wolfgang Roesner , Franz Hofmann
发明人： Michael Specht , Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L21/28282 , H01L21/76897 , H01L27/105 , H01L27/11568 , H01L29/66833 , H01L29/7851 , H01L29/792
摘要： The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.
摘要翻译：存储单元阵列包括多个平行翅片，它们设置成彼此相距约40nm的位线，并且具有小于约30nm的横向尺寸，被细分成相邻的第一和第二鳍片对。鳍片上布置有电荷俘获记忆层序列。词汇排列在翅片之间，源极/漏极区域位于字线之间的翅片和翅片的末端。优选地，在鳍片的端部处的源极/漏极区域的自对准接触区域，每个接触区域对于所述成对中的一个的翅片是共同的。选择晶体管，并且单独地为第一和第二散热片提供选择线以使得能够单独寻址存储器单元。

72. 发明申请

US20060108646A1 NROM semiconductor memory device and fabrication method 失效
标题翻译： NROM半导体存储器件及其制造方法
公开(公告)号：US20060108646A1
公开(公告)日：2006-05-25
申请号：US11282904
申请日：2005-11-18
申请人： Franz Hofmann , Erhard Landgraf , Michael Specht
发明人： Franz Hofmann , Erhard Landgraf , Michael Specht
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/66833 , H01L29/7923
摘要： This invention relates to a method for producing an NROM semiconductor memory device and a corresponding NROM semiconductor memory device. The inventive production method comprises the following steps: a plurality of spaced-apart U-shaped MOSFETS are provided along rows in a first direction and along gaps in a second direction inside trenches of a semiconductor substrate, said U-shaped MOSFETS comprising a multilayer dielectric, especially an ONO dielectric, for trapping charges; source/drain areas are provided between the U-shaped MOSFETS in intermediate spaces located between the rows that extend parallel to the gaps; insulating trenches are provided in the source/drain areas between the U-shaped MOSFETS of adjacent gaps, down to a certain depth in the semiconductor substrate, said insulating trenches cutting up the source/drain areas into respective bit lines; the insulating trenches are filled with an insulating material; and word lines are provided for connecting respective rows of U-shaped MOSFETS.
摘要翻译：本发明涉及一种制造NROM半导体存储器件和相应的NROM半导体存储器件的方法。本发明的制造方法包括以下步骤：在半导体衬底的沟槽内沿着第一方向并沿着第二方向的间隙沿着行设置多个间隔开的U形MOSFET，所述U形MOSFETS包括多层电介质，特别是用于捕获电荷的ONO电介质; 源极/漏极区域设置在位于平行于间隙延伸的行之间的中间空间中的U形MOSFET之间; 绝缘沟槽设置在相邻间隙的U形MOSFET之间的源极/漏极区域中，在半导体衬底内向下到达一定深度，所述绝缘沟槽将源极/漏极区域切割成相应的位线; 绝缘槽填充绝缘材料; 并且提供用于连接各行的U形MOSFET的字线。

73. 发明申请

US20050040456A1 Semiconductor memory element, production method and operational method 有权
标题翻译：半导体存储元件，生产方法和操作方法
公开(公告)号：US20050040456A1
公开(公告)日：2005-02-24
申请号：US10486184
申请日：2002-09-02
申请人： Michael Specht , Franz Hofmann
发明人： Michael Specht , Franz Hofmann
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L29/513 , G11C16/0416 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/518 , H01L29/66825 , H01L29/7883
摘要： A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the substrate, and a tunnel barrier arrangement, via which charging or discharging of the floating gate can be performed. It is possible to alter the conductivity of a channel between source and drain regions by charging or discharging the floating gate. A source line is electrically conductively connected to the source region and controls the charge transmission of the tunnel barrier arrangement.
摘要翻译：半导体存储元件具有形成源极区域和漏极区域的基板，与基板电绝缘的浮动栅极以及可以进行浮置栅极的充电或放电的隧道势垒装置。通过对浮动栅极进行充电或放电，可以改变源区和漏区之间的沟道的导电性。源极线导电地连接到源极区域并且控制隧道势垒装置的电荷传输。

74. 发明授权

US08097915B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08097915B2
公开(公告)日：2012-01-17
申请号：US11139976
申请日：2005-05-31
申请人： Wolfgang Rösner , Franz Hofmann , Michael Specht , Martin Städele , Johannes Luyken
发明人： Wolfgang Rösner , Franz Hofmann , Michael Specht , Martin Städele , Johannes Luyken
IPC分类号： H01L31/119
CPC分类号： H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7393
摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.
摘要翻译：半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极具有栅极电介质层和栅电极的结构。所述栅极结构布置在所述漏极区域和所述源极区域之间。提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。

75. 发明授权

US07915667B2 Integrated circuits having a contact region and methods for manufacturing the same 有权
标题翻译：具有接触区域的集成电路及其制造方法
公开(公告)号：US07915667B2
公开(公告)日：2011-03-29
申请号：US12137388
申请日：2008-06-11
申请人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
发明人： Roman Knoefler , Michael Specht , Franz Hofmann , Florian Beug , Dirk Manger , Stephan Riedel
IPC分类号： H01L29/792 , H01L29/788 , H01L21/336
CPC分类号： H01L21/28282 , H01L21/28273 , H01L21/8221 , H01L27/11565 , H01L27/11568 , H01L27/11578 , H01L27/11582 , H01L29/792 , H01L29/7926
摘要： In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.
摘要翻译：在一个实施例中，提供了具有存储单元布置的集成电路。存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移基材的主要加工表面。

76. 发明授权

US07714377B2 Integrated circuits and methods of manufacturing thereof 有权
标题翻译：集成电路及其制造方法
公开(公告)号：US07714377B2
公开(公告)日：2010-05-11
申请号：US11737617
申请日：2007-04-19
申请人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
发明人： Michael Specht , Nicolas Nagel , Franz Hofmann , Thomas Mikolajick
IPC分类号： H01L29/788
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , Y10T29/49117
摘要： Embodiments of the invention relate to integrated circuits having a memory cell arrangement and methods of manufacturing thereof. In one embodiment of the invention, an integrated circuit has a memory cell arrangement which includes a fin structure extending in its longitudinal direction as a first direction, including a first insulating layer, a first active region disposed above the first insulating layer, a second insulating layer disposed above the first active region, a second active region disposed above the second insulating layer, a charge storage layer structure disposed at least next to at least one sidewall of the fin structure covering at least a portion of the first active region and at least a portion of the second active region, and a control gate disposed next to the charge storage layer structure.
摘要翻译：本发明的实施例涉及具有存储单元布置的集成电路及其制造方法。在本发明的一个实施例中，集成电路具有存储单元布置，其包括沿其纵向方向延伸的翅片结构作为第一方向，包括第一绝缘层，设置在第一绝缘层上方的第一有源区，第二绝缘层设置在所述第一有源区上方的第二有源区，设置在所述第二绝缘层上方的第二有源区，电荷存储层结构，其至少布置在所述鳍结构的至少一个侧壁上，覆盖所述第一有源区的至少一部分，并且至少第二有源区的一部分，以及设置在电荷存储层结构旁边的控制栅。

77. 发明申请

US20090261397A1 Integrated Circuit with Floating-Gate Electrodes Including a Transition Metal and Corresponding Manufacturing Method 有权
标题翻译：具有过渡金属的浮栅电极集成电路及相应的制造方法
公开(公告)号：US20090261397A1
公开(公告)日：2009-10-22
申请号：US12104750
申请日：2008-04-17
申请人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
发明人： Josef Willer , Franz Hofmann , Michael Specht , Christoph Friederich , Doris Keitel-Schulz , Lars Bach , Thomas Melde
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521
摘要： An integrated circuit is described. The integrated circuit may comprise a multitude of floating-gate electrodes, wherein at least one of the floating-gate electrodes has a lower width and an upper width, the lower width being larger than the upper width, and wherein the at least one of the floating-gate electrodes comprises a transition metal. A corresponding manufacturing method for an integrated circuit is also described.
摘要翻译：描述了集成电路。集成电路可以包括多个浮栅电极，其中浮栅电极中的至少一个具有较低宽度和上宽度，下宽度大于上宽度，并且其中至少一个浮栅电极包括过渡金属。还描述了集成电路的相应制造方法。

78. 发明申请

US20080308856A1 Integrated Circuit Having a Fin Structure 失效
标题翻译：具有鳍结构的集成电路
公开(公告)号：US20080308856A1
公开(公告)日：2008-12-18
申请号：US11762582
申请日：2007-06-13
申请人： Michael Specht , Franz Hofmann , Wolfgang Roesner , Guerkan Ilicali
发明人： Michael Specht , Franz Hofmann , Wolfgang Roesner , Guerkan Ilicali
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792
CPC分类号： H01L27/115 , H01L25/0657 , H01L27/11521 , H01L27/11568 , H01L29/66818 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention relate generally to a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement, an integrated circuit, a cell arrangement, and a memory module. In an embodiment of the invention, a method for manufacturing an integrated circuit having a cell arrangement is provided, including forming at least one semiconductor fin structure having an area for a plurality of fin field effect transistors, wherein the area of each fin field effect transistor includes a first region having a first fin structure width, a second region having a second fin structure width, wherein the second fin structure width is smaller than the first fin structure width. Furthermore, a plurality of charge storage regions are formed on or above the second regions of the semiconductor fin structure.
摘要翻译：本发明的实施例一般涉及用于制造集成电路的方法，用于制造单元布置的方法，集成电路，单元布置和存储器模块。在本发明的一个实施例中，提供一种用于制造具有单元布置的集成电路的方法，包括形成至少一个半导体鳍结构，其具有用于多个鳍场效应晶体管的面积，其中每个鳍场效应晶体管的面积包括具有第一鳍结构宽度的第一区域，具有第二鳍结构宽度的第二区域，其中第二鳍结构宽度小于第一鳍结构宽度。此外，在半导体鳍片结构的第二区域上或上方形成多个电荷存储区域。

79. 发明授权

US07298004B2 Charge-trapping memory cell and method for production 有权
标题翻译：电荷俘获记忆体和生产方法
公开(公告)号：US07298004B2
公开(公告)日：2007-11-20
申请号：US11000350
申请日：2004-11-30
申请人： Michael Specht , Wolfgang Roesner , Franz Hofmann
发明人： Michael Specht , Wolfgang Roesner , Franz Hofmann
IPC分类号： H01L29/788
CPC分类号： H01L21/76895 , H01L21/28282 , H01L21/76897 , H01L27/105 , H01L27/11568 , H01L29/66833 , H01L29/7851 , H01L29/792
摘要： The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.
摘要翻译：存储单元阵列包括多个平行翅片，它们设置成彼此相距约40nm的位线，并且具有小于约30nm的横向尺寸，被细分成相邻的第一和第二鳍片对。鳍片上布置有电荷俘获记忆层序列。词汇排列在翅片之间，源极/漏极区域位于字线之间的翅片和翅片的末端。优选地，在鳍片的端部处的源极/漏极区域的自对准接触区域，每个接触区域对于所述成对中的一个的翅片是共同的。选择晶体管，并且单独地为第一和第二散热片提供选择线以使得能够单独寻址存储器单元。

80. 发明授权

US07195978B2 Method for the production of a memory cell, memory cell and memory cell arrangement 有权
标题翻译：用于生产存储器单元，存储单元和存储单元布置的方法
公开(公告)号：US07195978B2
公开(公告)日：2007-03-27
申请号：US10999810
申请日：2004-11-29
申请人： Franz Hofmann , Richard Johannes Luyken , Michael Specht
发明人： Franz Hofmann , Richard Johannes Luyken , Michael Specht
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L21/28273 , G11C16/0416 , G11C16/0483 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/7881 , H01L29/7883
摘要： Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an electrically insulating layer formed on the floating gate, a memory gate electrode formed on the electrically insulating layer, a substrate fixed to the memory gate electrode, a second gate insulating layer formed on a part of a surface of the auxiliary substrate, which surface is uncovered by partially removing the auxiliary substrate, a read gate electrode formed on the second gate insulating layer, and two source/drain regions located essentially in a surface region of the remaining material of the auxiliary substrate that is free of the second gate insulating layer and the read gate electrode, a channel region located between the two source/drain regions, wherein the channel region at least partly laterally overlaps the floating gate and the read gate electrode.
摘要翻译：具有辅助基板的存储单元，其上形成有第一栅极绝缘层，形成在第一栅极绝缘层上的浮动栅极，形成在浮动栅极上的电绝缘层，形成在电绝缘层上的存储栅电极，基板固定到存储栅电极，第二栅极绝缘层，形成在辅助基板的表面的一部分上，该表面通过部分去除辅助基板而被覆盖，形成在第二栅极绝缘层上的读取栅电极和两个源极/漏极区域基本上位于辅助衬底的不含第二栅极绝缘层和读取栅电极的剩余材料的表面区域中，位于两个源极/漏极区域之间的沟道区域，其中沟道区域在至少部分地侧向重叠浮置栅极和读取栅电极。

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