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71. 发明授权

US06878918B2 APS pixel with reset noise suppression and programmable binning capability 有权
标题翻译：具有复位噪声抑制和可编程合并能力的APS像素
公开(公告)号：US06878918B2
公开(公告)日：2005-04-12
申请号：US10339189
申请日：2003-01-09
申请人： Taner Dosluoglu
发明人： Taner Dosluoglu
IPC分类号： H01L27/14 , H01L27/00 , H01L27/146 , H01L31/10 , H04N3/15 , H04N5/335
CPC分类号： H04N5/37457 , H01L27/14603 , H01L27/14609 , H01L27/14643 , H04N5/347 , H04N5/3577 , H04N5/374
摘要： A circuit and method are described which suppresses reset noise in active pixel sensor arrays. A circuit having a number of N− wells formed in a P− silicon epitaxial layer or a number of P− wells formed in an N− silicon epitaxial layer is provided. A pixel is formed in each of the wells so that each of the wells is surrounded by silicon of the opposite polarity and an array of pixels is formed. Means are provided for selectively combining or binning adjacent N− or P− wells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated. The reset is accomplished using a PMOS transistor formed in each N− well or an NMOS transistor formed in each P− well. The selective binning is accomplished using NMOS or PMOS transistors formed in the region between adjacent wells. Conductive traces between adjacent wells can also be used to accomplish the selective binning.
摘要翻译：描述了抑制有源像素传感器阵列中的复位噪声的电路和方法。提供了在N - 硅外延层中形成的在多个硅外延层或多个P阱中形成的N个阱的电路。在每个阱中形成像素，使得每个阱由相反极性的硅包围并形成像素阵列。提供了用于选择性地组合或合并相邻的N或P阱的装置。在成像周期的复位周期期间，选择的相邻像素组被合并，并且通过像素的复位注入的电荷在相邻像素之间被平均化，由此减小了该电荷注入对任何一个像素的影响，从而减少产生噪音使用在每个N阱中形成的PMOS晶体管或在每个P阱中形成的NMOS晶体管来实现复位。使用形成在相邻阱之间的区域中的NMOS或PMOS晶体管来实现选择性分级。相邻孔之间的导电迹线也可用于完成选择性分样。

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