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71. 发明申请

US20120305940A1 Defect Free Si:C Epitaxial Growth 审中-公开
标题翻译：缺陷Si：C外延生长
公开(公告)号：US20120305940A1
公开(公告)日：2012-12-06
申请号：US13151238
申请日：2011-06-01
申请人： Thomas N. Adam , Stephen W. Bedell , Bruce B. Doris , Lisa F. Edge , Keith E. Fogel , Johnathan E. Faltermeier , Jinghong Li , Alexander Reznicek , Devendra K. Sadana , Bin Yang
发明人： Thomas N. Adam , Stephen W. Bedell , Bruce B. Doris , Lisa F. Edge , Keith E. Fogel , Johnathan E. Faltermeier , Jinghong Li , Alexander Reznicek , Devendra K. Sadana , Bin Yang
IPC分类号： H01L29/24 , H01L21/20
CPC分类号： H01L21/02529 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L29/045 , H01L29/66636 , H01L29/7848 , H01L29/78654
摘要： A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.
摘要翻译：公开了在NFET器件中的无缺陷Si：C源极/漏极的方法和结构。接受具有{100}晶体取向的主表面的晶片。以这样的方式在晶片中形成凹部，使得凹部的底表面和四个侧壁表面都具有{100}晶体取向。 Si：C材料在凹槽中被轴向生长，并且由于晶体取向，邻近四个侧壁表面的缺陷密度基本上与下表面相同。外延填充的凹槽用于NFET器件的源极/漏极制造。 NFET器件沿着<100>结晶方向取向，由于源极/漏极中的缺陷Si：C，器件沟道处于拉伸应变状态。

72. 发明授权

US07897444B2 Strained semiconductor-on-insulator (sSOI) by a simox method 有权
标题翻译：应用绝缘体半导体（sSOI）通过simox方法
公开(公告)号：US07897444B2
公开(公告)日：2011-03-01
申请号：US12363239
申请日：2009-01-30
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L21/84
CPC分类号： H01L21/76243 , H01L29/66772 , H01L29/7849 , H01L29/78654
摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.
摘要翻译：提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

73. 发明授权

US07592671B2 Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer 失效
标题翻译：通过掩埋的p +硅锗层的阳极氧化应变的绝缘体上硅
公开(公告)号：US07592671B2
公开(公告)日：2009-09-22
申请号：US11620663
申请日：2007-01-06
申请人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
发明人： Thomas N. Adam , Stephen W. Bedell , Joel P. de Souza , Keith E. Fogel , Alexander Reznicek , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L29/94
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

74. 发明授权

US09053939B2 Heterojunction bipolar transistor with epitaxial emitter stack to improve vertical scaling 有权
标题翻译：具有外延发射极堆叠的异质结双极晶体管，以改善垂直刻度
公开(公告)号：US09053939B2
公开(公告)日：2015-06-09
申请号：US13303248
申请日：2011-11-23
申请人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
发明人： Thomas N. Adam , David L. Harame , Qizhi Liu , Alexander Reznicek
IPC分类号： H01L29/737 , H01L21/02 , H01L29/66 , H01L29/08 , H01L29/417 , H01L29/10
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02521 , H01L21/02529 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L29/0817 , H01L29/1004 , H01L29/41708 , H01L29/66242 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.
摘要翻译：异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。

75. 发明申请

US20140027863A1 MERGED FIN FINFET WITH (100) SIDEWALL SURFACES AND METHOD OF MAKING SAME 有权
标题翻译：具有（100）面板表面的合并FIN FINFET及其制造方法
公开(公告)号：US20140027863A1
公开(公告)日：2014-01-30
申请号：US13561352
申请日：2012-07-30
申请人： Thomas N. Adam , Keith E. Fogel , Jinghong Li , Alexander Reznicek
发明人： Thomas N. Adam , Keith E. Fogel , Jinghong Li , Alexander Reznicek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/16 , H01L29/161 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66795
摘要： A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.
摘要翻译：翅片finFET和其制造方法。鳍状FET包括：在半导体衬底上的绝缘层的顶表面上的两个或多个单晶半导体鳍片，两个或更多鳍片的每个翅片具有位于第一和第二端部区域之间的中间区域和相对的两侧，顶表面并且两个或更多个翅片的侧壁是（100）表面，并且两个或更多个翅片的纵向轴线与[100]方向对准; 在两个或更多个翅片的每个翅片上的栅介质层; 在两个或更多个翅片的每个翅片的中心区域上方的栅极电介质层上的导电栅极; 以及合并的源极/漏极，其包括在两个或更多个鳍片的每个鳍片的端部上的连续的外延半导体材料层，其端部位于导电栅极的同一侧。

76. 发明申请

US20120326168A1 TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE 审中-公开
标题翻译：带有硅锗锗的晶体管，用于改进的近似控制和优化的形状
公开(公告)号：US20120326168A1
公开(公告)日：2012-12-27
申请号：US13608250
申请日：2012-09-10
申请人： Thomas N. Adam , Judson R. Holt , Alexander Reznicek , Thomas A. Wallner
发明人： Thomas N. Adam , Judson R. Holt , Alexander Reznicek , Thomas A. Wallner
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/66636 , H01L29/66742 , H01L29/7848 , H01L29/78687
摘要： A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.
摘要翻译：一种形成半导体器件的方法，包括在含锗硅层上提供包括半导体层的衬底，并在半导体层的沟道部分的表面上形成栅极结构。阱沟槽被蚀刻到栅极结构的相对侧上的半导体层中。用于形成阱沟槽的蚀刻工艺形成在栅极结构下延伸的底切区域，并且对含锗硅层具有选择性。应力诱导半导体材料被外延生长以填充阱沟槽的至少一部分以提供应力诱导源区域和具有平面基极的应力诱导漏极区域中的至少一个。

77. 发明申请

US20120319166A1 TRANSISTOR WITH BURIED SILICON GERMANIUM FOR IMPROVED PROXIMITY CONTROL AND OPTIMIZED RECESS SHAPE 有权
公开(公告)号：US20120319166A1
公开(公告)日：2012-12-20
申请号：US13161913
申请日：2011-06-16
申请人： Thomas N. Adam , Judson R. Holt , Alexander Reznicek , Thomas A. Wallner
发明人： Thomas N. Adam , Judson R. Holt , Alexander Reznicek , Thomas A. Wallner
IPC分类号： H01L29/78 , H01L29/04 , H01L21/336
CPC分类号： H01L29/1054 , H01L29/045 , H01L29/66636 , H01L29/66742 , H01L29/7848 , H01L29/78687
摘要： A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.

78. 发明申请

US20120205716A1 Epitaxially Grown Extension Regions for Scaled CMOS Devices 审中-公开
标题翻译：用于缩放CMOS器件的外延生长扩展区
公开(公告)号：US20120205716A1
公开(公告)日：2012-08-16
申请号：US13028316
申请日：2011-02-16
申请人： Thomas N. Adam , Jeffrey B. Johnson , Pranita Kulkarni , Douglas C. LaTulipe, JR. , Alexander Reznicek
发明人： Thomas N. Adam , Jeffrey B. Johnson , Pranita Kulkarni , Douglas C. LaTulipe, JR. , Alexander Reznicek
IPC分类号： H01L29/165 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7848
摘要： Epitaxially grown extension regions are disclosed for scaled CMOS devices. Semiconductor devices are provided that comprise a field effect transistor (FET) structure having a gate stack on a silicon substrate, wherein the field effect transistor structure comprises at least a channel layer formed below the gate stack. One or more etched extension regions containing an epitaxially grown dopant are provided in the channel layer.
摘要翻译：公开了用于缩放CMOS器件的外延生长扩展区。提供了包括在硅衬底上具有栅极堆叠的场效应晶体管（FET）结构的半导体器件，其中场效应晶体管结构至少包括形成在栅极堆叠下方的沟道层。在沟道层中设置一个或多个含有外延生长掺杂剂的蚀刻延伸区。

79. 发明申请

US20120003819A1 Methods and apparatus for selective epitaxy of si-containing materials and substitutionally doped crystalline si-containing material 有权
标题翻译：用于选择性外延Si含量材料和替代掺杂晶体含Si材料的方法和设备
公开(公告)号：US20120003819A1
公开(公告)日：2012-01-05
申请号：US13135031
申请日：2011-06-23
申请人： Terry Arthur Francis , Satoshi Hasaka , Paul David Brabant , Robert Torres, JR. , He Hong , Alexander Reznicek , Thomas N. Adam , Devendra K. Sadana
发明人： Terry Arthur Francis , Satoshi Hasaka , Paul David Brabant , Robert Torres, JR. , He Hong , Alexander Reznicek , Thomas N. Adam , Devendra K. Sadana
IPC分类号： H01L21/205
CPC分类号： H01L21/02532 , C23C16/30 , C23C16/325 , C30B25/02 , C30B29/06 , H01L21/0237 , H01L21/02529 , H01L21/02573 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636
摘要： The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.
摘要翻译：本发明公开了在改进的化学气相沉积（mCVD）条件下，外延硅膜可以通过将包含在腔室内的衬底暴露于相对高的载气流量与在较低的硅前体流速小于约550℃，压力范围为约10mTorr-200Torr。此外，通过在改进的CVD条件下使用四硅烷作为硅源和含碳气体如十二烷基甲基环己硅烷或四甲基二硅烷以相对高的流速进行沉积，可以将晶体Si原位掺杂以含有相对高水平的取代碳。

80. 发明授权

US08946033B2 Merged fin finFET with (100) sidewall surfaces and method of making same 有权
标题翻译：具有（100）侧壁表面的合并翅片finFET及其制造方法
公开(公告)号：US08946033B2
公开(公告)日：2015-02-03
申请号：US13561352
申请日：2012-07-30
申请人： Thomas N. Adam , Keith E. Fogel , Jinghong Li , Alexander Reznicek
发明人： Thomas N. Adam , Keith E. Fogel , Jinghong Li , Alexander Reznicek
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/785 , H01L29/16 , H01L29/161 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66795
摘要： A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.
摘要翻译：翅片finFET和其制造方法。鳍状FET包括：在半导体衬底上的绝缘层的顶表面上的两个或多个单晶半导体鳍片，两个或更多鳍片的每个翅片具有位于第一和第二端部区域之间的中间区域和相对的两侧，顶表面并且两个或更多个翅片的侧壁是（100）表面，并且两个或更多个翅片的纵向轴线与[100]方向对准; 在两个或更多个翅片的每个翅片上的栅介质层; 在两个或更多个翅片的每个翅片的中心区域上方的栅极电介质层上的导电栅极; 以及合并的源极/漏极，其包括在两个或更多个鳍片的每个鳍片的端部上的连续的外延半导体材料层，其端部位于导电栅极的同一侧。

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