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71. 发明申请

US20210193194A1 CONTROL METHOD FOR MEMORY DEVICE 有权
公开(公告)号：US20210193194A1
公开(公告)日：2021-06-24
申请号：US17197632
申请日：2021-03-10
申请人： TOSHIBA MEMORY CORPORATION
发明人： Ryota SUZUKI , Tatsuo Izumi
IPC分类号： G11C5/14 , G11C11/56 , G11C29/50 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/30 , G11C16/34 , H01L27/115
摘要： According to one embodiment, a method of controlling a memory device includes supplying a second potential having a first value to a second electrode and simultaneously, or thereafter, supplying a third potential to a third electrode, and thereafter stopping supply of the third potential such that the potential of the third electrode decays while reducing the potential of the second electrode, and thereafter supplying a first potential to the first electrode.

72. 发明授权

US11043419B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US11043419B2
公开(公告)日：2021-06-22
申请号：US16294044
申请日：2019-03-06
申请人： TOSHIBA MEMORY CORPORATION
发明人： Ippei Kume
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48 , H01L21/48 , H01L21/311 , H01L23/538
摘要： A semiconductor device according to an embodiment comprises a semiconductor substrate having a through hole from a first face to a second face on an opposite side to the first face. A metal part is provided inside the through hole. A stacked film is provided between the metal part and an inner side surface of the through hole, and comprises a plurality of different material films of two or more types having a relative permittivity equal to or lower than 6.5.

73. 发明授权

US11042487B2 Memory system and method for controlling nonvolatile memory 有权
公开(公告)号：US11042487B2
公开(公告)日：2021-06-22
申请号：US16555663
申请日：2019-08-29
申请人： Toshiba Memory Corporation
发明人： Hideki Yoshida , Shinichi Kanno
IPC分类号： G06F12/1009 , G06F12/02
摘要： According to one embodiment, a memory system receives a write request specifying a first logical address to which first data is to be written, and a length of the first data, from a host. The memory system writes the first data to a nonvolatile memory, and stores a first physical address indicating a physical storage location on the nonvolatile memory to which the first data is written, and the length of the first data, in an entry of a logical-to-physical address translation table corresponding to the first logical address. When the memory system receives a read request specifying the first logical address, the memory system acquires the first physical address and the length from the address translation table, and reads the first data from the nonvolatile memory.

74. 发明授权

US11042321B2 Memory controller 有权
公开(公告)号：US11042321B2
公开(公告)日：2021-06-22
申请号：US16552821
申请日：2019-08-27
申请人： TOSHIBA MEMORY CORPORATION
发明人： Daisuke Uchida
IPC分类号： G06F3/06
摘要： A memory controller that controls a nonvolatile memory in response to commands from a host, includes a normal transfer queue and a priority transfer queue, a transfer packet priority determination unit, a transfer queue selector, and a transfer packet selector. The transfer packet priority determination unit determines whether a transfer packet is a priority packet based on transmission information of the transfer packet. The transfer queue selector selects the priority transfer queue and stores the transfer packet in the priority transfer queue when the transfer packet is determined as the priority packet, and selects the normal transfer queue and stores the transfer packet in the normal transfer queue when the transfer packet is not determined as the priority packet. The transfer packet selector transfers to a host a priority packet stored in the priority transfer queue preferentially with respect to a normal packet stored in the normal transfer queue.

75. 发明授权

US11042300B2 Command load balancing for NVME dual port operations 有权
公开(公告)号：US11042300B2
公开(公告)日：2021-06-22
申请号：US14674632
申请日：2015-03-31
申请人： Toshiba Memory Corporation
发明人： Sancar Kunt Olcay , Dishi Lai
IPC分类号： G06F3/00 , G06F3/06 , G06F12/06
摘要： In an example, a method of processing commands for a non-volatile storage device includes storing the commands among a plurality of first-level queues in a random access memory (RAM). Each command is assigned to a first-level queue based on membership in one of a plurality of first-level categories. The method further includes removing selected commands from the plurality of first-level queues according to a first schedule and performing at least one operation on the selected commands. The method further includes storing the selected commands among a plurality of second-level queues in the RAM. Each selected command is assigned to a second-level queue based on whether the command is a read command or a write command. The method further includes removing active commands from the plurality of second-level queues according to a second schedule. The method further includes issuing the active commands to a back end of the controller for processing.

76. 发明申请

US20210183881A1 SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20210183881A1
公开(公告)日：2021-06-17
申请号：US17184094
申请日：2021-02-24
申请人： Toshiba Memory Corporation
发明人： Hidenobu NAGASHIMA
IPC分类号： H01L27/11575 , H01L27/11573 , H01L21/762 , H01L27/11565 , H01L23/535 , H01L21/768 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.

77. 发明申请

US20210174876A1 SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES 有权
公开(公告)号：US20210174876A1
公开(公告)日：2021-06-10
申请号：US17180938
申请日：2021-02-22
申请人： TOSHIBA MEMORY CORPORATION
发明人： Noboru SHIBATA , Hiroshi SUKEGAWA
IPC分类号： G11C16/10 , G11C16/16 , G11C16/26 , G11C16/08 , G11C16/34 , G11C16/04 , G11C11/56 , G11C16/30
摘要： A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

78. 发明授权

US11030043B2 Error correction circuit and memory system 有权
公开(公告)号：US11030043B2
公开(公告)日：2021-06-08
申请号：US16569369
申请日：2019-09-12
申请人： TOSHIBA MEMORY CORPORATION
发明人： Kosuke Hatsuda
IPC分类号： G06F11/10 , H03M13/15
摘要： An error correction circuit includes a syndrome calculator to calculate syndrome information of input data, an error position calculator to calculate error position information of the input data, a holder to hold the syndrome information or the error position information at a predetermined timing, an input switch to select one of error-corrected data of the input data, and the input data, and to input the selected data to the syndrome calculator, an error detection determiner to determine whether an error of the input data has been correctly detected, and an error corrector to correct the error of the input data based on information held by the holder and to output error-corrected input data when it is determined by the error detection determiner that the error has been correctly detected whereas to output the input data with no error correction when it is determined by the error detection determiner.

79. 发明授权

US11029859B2 Credit based command scheduling 有权
公开(公告)号：US11029859B2
公开(公告)日：2021-06-08
申请号：US15684076
申请日：2017-08-23
申请人： Toshiba Memory Corporation
发明人： Julien Margetts , Hyoun Kwon Jeong , Jonghyeon Kim
IPC分类号： G06F3/06 , G06F13/16 , G06F13/20 , G06F13/40 , G06F1/329 , G06F1/3234 , G06F1/3225
摘要： A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.

80. 发明申请

US20210167176A1 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE 有权
公开(公告)号：US20210167176A1
公开(公告)日：2021-06-03
申请号：US16492342
申请日：2019-03-12
申请人： TOSHIBA MEMORY CORPORATION
发明人： Tomoya INDEN , Katsuyuki KITAMOTO
IPC分类号： H01L29/417 , H01L23/535 , H01L29/40
摘要： An integrated circuit device of an embodiment includes a substrate, a first transistor, an insulation layer, a first contact, a second contact, and a first single crystal portion. The first transistor includes a first gate electrode, and a first drain region, and wherein the first source region and the first drain region are disposed in the substrate. The first contact faces the first gate electrode. The second contact faces a first region that is first one of the first source region and the first drain region. The first single crystal portion is disposed on the first region and convex from a surface of the first region, and is located between the first region and the second contact.

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