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71. 发明授权

US07949931B2 Systems and methods for error detection in a memory system 有权
标题翻译：用于存储系统中错误检测的系统和方法
公开(公告)号：US07949931B2
公开(公告)日：2011-05-24
申请号：US11619015
申请日：2007-01-02
申请人： Luis A. Lastras-Montano
发明人： Luis A. Lastras-Montano
IPC分类号： H03M13/00
CPC分类号： H03M13/1515 , G06F11/1044 , H03M13/159 , H03M13/3715
摘要： A method for error detection in a memory system. The method includes calculating one or more signatures associated with data that contains an error. It is determined if the error is a potential correctable error. If the error is a potential correctable error, then the calculated signatures are compared to one or more signatures in a trapping set. The trapping set includes signatures associated with uncorrectable errors. An uncorrectable error flag is set in response to determining that at least one of the calculated signatures is equal to a signature in the trapping set.
摘要翻译：一种存储系统中的错误检测方法。该方法包括计算与包含错误的数据相关联的一个或多个签名。确定错误是否是潜在的可纠正错误。如果错误是潜在的可纠正错误，则将计算的签名与陷阱集中的一个或多个签名进行比较。陷阱集包括与不可纠正错误相关联的签名。响应于确定所计算的签名中的至少一个等于捕获集合中的签名，设置不可校正的错误标志。

72. 发明申请

US20100293437A1 System to Improve Memory Failure Management and Associated Methods 失效
标题翻译：改善内存故障管理和相关方法的系统
公开(公告)号：US20100293437A1
公开(公告)日：2010-11-18
申请号：US12023498
申请日：2008-01-31
申请人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
发明人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/353 , H03M13/3707 , H03M13/6511
摘要： A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
摘要翻译：改善存储器故障管理的系统可以包括存储器和用于确定存储器中的故障的错误控制解码器。系统还可以包括可以监视存储器中的故障的代理。该系统还可以包括一个表，其中错误控制解码器可以记录故障，以及代理可以在哪里读写。

73. 发明申请

US20100287454A1 System to Improve Error Code Decoding Using Historical Information and Associated Methods 有权
标题翻译：使用历史信息和相关方法改进错误代码解码的系统
公开(公告)号：US20100287454A1
公开(公告)日：2010-11-11
申请号：US12023445
申请日：2008-01-31
申请人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
发明人： Timothy J. Dell , Luis A. Lastras-Montano , Barry M. Trager , Shmuel Winograd
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve error code decoding using historical information may include storage partitioned into memory ranks, and a table to record symbols having failures for each memory rank. The system may also generate a memory rank score for each memory rank. The system may also include an error control decoder that may use the memory rank score when each memory rank is accessed in order to determine whether an error should be corrected or not.
摘要翻译：使用历史信息改进错误代码解码的系统可以包括分割成存储器排名的存储器，以及记录具有每个存储器级别故障的符号的表。系统还可以为每个存储器等级产生存储器等级分数。系统还可以包括错误控制解码器，其可以在访问每个存储器级时使用存储器等级分数，以便确定是否应该纠正错误。

74. 发明申请

US20100214829A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20100214829A1
公开(公告)日：2010-08-26
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

75. 发明申请

US20090254705A1 BUS ATTACHED COMPRESSED RANDOM ACCESS MEMORY 审中-公开
标题翻译：总线连接压缩随机存取存储器
公开(公告)号：US20090254705A1
公开(公告)日：2009-10-08
申请号：US12098900
申请日：2008-04-07
申请人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
发明人： Bulent Abali , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/0897 , G06F2212/2022 , G06F2212/2024 , G06F2212/401
摘要： A computer memory system having a three-level memory hierarchy structure is disclosed. The system includes a memory controller, a volatile memory, and a non-volatile memory. The volatile memory is divided into an uncompressed data region and a compressed data region.
摘要翻译：公开了一种具有三级存储器层次结构的计算机存储器系统。该系统包括存储器控制器，易失性存储器和非易失性存储器。易失性存储器被分为未压缩数据区和压缩数据区。

76. 发明授权

US07471219B1 Low latency constrained coding for parallel busses 失效
标题翻译：并行总线的低延迟约束编码
公开(公告)号：US07471219B1
公开(公告)日：2008-12-30
申请号：US11846795
申请日：2007-08-29
申请人： Luis A. Lastras-Montano
发明人： Luis A. Lastras-Montano
IPC分类号： H03M7/02
CPC分类号： G06F13/4208 , Y02D10/14 , Y02D10/151
摘要： A system and method for providing low latency constrained coding for parallel busses. The method includes receiving a value for a number of transfers and a number of possible constrained patterns between adjacent transfer rows. Data to be encoded is received. The data is converted into indices of constrained patterns, the converting including a number base change into a new base. The new base is chosen so as to optimize the number of operations required to perform the converting subject to the new base being at least as large as the number of possible constrained patterns between adjacent transfer rows. The indices of the constrained pattern are converted into encoded data. The encoded data is then output.
摘要翻译：一种用于为并行总线提供低延迟约束编码的系统和方法。该方法包括在相邻的传输行之间接收多个传输的数值和可能的约束模式的数量。接收要编码的数据。数据被转换为约束模式的索引，转换包括基数变换为新的基数。选择新的基座，以便将执行转换对象所需的操作数量优化为至少与相邻传送行之间的可能约束模式的数量一样大的新基址。约束模式的索引被转换为编码数据。然后输出编码数据。

77. 发明授权

US09881099B2 System, method and computer program product for data transfer management 有权
公开(公告)号：US09881099B2
公开(公告)日：2018-01-30
申请号：US12786072
申请日：2010-05-24
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Danie M. Dreps , Luis A Lastras-Montano , Michael J Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Danie M. Dreps , Luis A Lastras-Montano , Michael J Shapiro
IPC分类号： G06F17/30 , G06F12/00 , G06K9/62
CPC分类号： G06F17/30899 , G06F17/30259 , G06K9/6202
摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.

78. 发明授权

US08990217B2 Lossless compression of high nominal-range data 有权
标题翻译：高标称范围数据的无损压缩
公开(公告)号：US08990217B2
公开(公告)日：2015-03-24
申请号：US13181880
申请日：2011-07-13
申请人： Ashish Jagmohan , Joshua W. Knight , Luis A. Lastras-Montano
发明人： Ashish Jagmohan , Joshua W. Knight , Luis A. Lastras-Montano
IPC分类号： G06F17/30 , H03M7/30
CPC分类号： H03M7/3084 , G06F17/30613 , G06F2212/401
摘要： A method for receiving a data stream that includes data samples, each data sample having one of a plurality of actual values. For each data sample in the data stream, a first index in a dictionary is selected. The dictionary includes indices corresponding to each of the plurality of actual values. The first index corresponds to an actual value of the data sample. A predicted value of the data sample is generated in response to previously received data samples in the data stream and to a prediction algorithm. A second index in the dictionary that corresponds to an actual value in the dictionary that is closest to the value of the predicted value is selected. The difference between the first index and the second index is calculated and compressed. The compressed difference between the first index and the second index is then output. This process is performed for each data sample in the data stream.
摘要翻译：一种用于接收包括数据样本的数据流的方法，每个数据样本具有多个实际值中的一个。对于数据流中的每个数据样本，选择字典中的第一个索引。字典包括与多个实际值中的每一个对应的索引。第一个索引对应于数据样本的实际值。响应于先前接收的数据流中的数据样本和预测算法产生数据样本的预测值。选择字典中对应于字典中与预测值的值最接近的实际值的第二索引。计算并压缩第一个索引和第二个索引之间的差异。然后输出第一索引和第二索引之间的压缩差。对数据流中的每个数据样本执行此过程。

79. 发明授权

US08874846B2 Memory cell presetting for improved memory performance 有权
标题翻译：内存单元预置，以提高内存性能
公开(公告)号：US08874846B2
公开(公告)日：2014-10-28
申请号：US13619451
申请日：2012-09-14
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
摘要翻译：用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值存储器单元的指定状态到存储器单元的期望状态。第二期望值比第一期望值更接近写入性能特性的期望值。区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

80. 发明授权

US08806295B2 Mis-correction and no-correction rates for error control 有权
标题翻译：误差校正和无校正率
公开(公告)号：US08806295B2
公开(公告)日：2014-08-12
申请号：US13479855
申请日：2012-05-24
申请人： Ashish Jagmohan , Luis A. Lastras-Montano
发明人： Ashish Jagmohan , Luis A. Lastras-Montano
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/1008 , H03M13/1515
摘要： An embodiment is a method for encoding data with an error correction code. The method includes receiving a first number of data symbols by a memory controller, receiving a second number of meta-data sub-symbols, generating a third number of check symbols using an ECC, where the third number includes a difference between a number of symbols in an ECC codeword and the first number and generating a mismatch vector from the check and meta-data sub-symbols, where a number of sub-symbols of the mismatch vector includes the second number. The method also includes generating an adjustment syndrome symbol by multiplying the mismatch vector by a matrix, generating the third number of adjusted check symbols responsive to the adjustment syndrome symbol, and generating a final codeword by concatenating the adjusted check symbols and the data symbols, where the final codeword includes the number of symbols in the ECC codeword.
摘要翻译：实施例是用纠错码对数据进行编码的方法。该方法包括由存储器控制器接收第一数量的数据符号，接收第二数量的元数据子符号，使用ECC生成第三数量的校验符号，其中第三数字包括多个符号之间的差异在ECC码字和第一数字中，并且从校验和元数据子符号生成不匹配向量，其中失配向量的子数目的数目包括第二数目。该方法还包括通过将失配向量乘以矩阵来产生调整校正符号符号，响应于调整校正子符号产生第三数量的经调整的校验符号，以及通过连接调整的校验符号和数据符号来生成最终码字，其中最终码字包括ECC码字中的符号数。

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