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71. 发明申请

US20110026318A1 ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS 有权
标题翻译：迭代写暂停技术来改善读取存储器系统的延迟
公开(公告)号：US20110026318A1
公开(公告)日：2011-02-03
申请号：US12533548
申请日：2009-07-31
申请人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
发明人： Michele M. Franceschini , Luis A. Lastras-Montano , Moinuddin K. Qureshi , Vijayalakshmi Srinivasan
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G06F13/1642 , G06F13/161
摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.
摘要翻译：迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。恢复响应于保存的状态和要写入的数据。

72. 发明申请

US20100299576A1 System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods 失效
标题翻译：系统通过缓冲和相关方法提高错误控制代码的误码率
公开(公告)号：US20100299576A1
公开(公告)日：2010-11-25
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译：用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。

73. 发明申请

US20100281340A1 ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的自适应耐久编码
公开(公告)号：US20100281340A1
公开(公告)日：2010-11-04
申请号：US12433669
申请日：2009-04-30
申请人： MIchele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： MIchele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/05 , G06F12/00 , G06F11/10 , G06F17/30
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.
摘要翻译：自适应耐力编码包括用于存储包括接收写入数据和写入地址的数据的方法。将压缩算法应用于写入数据以生成压缩数据。将耐力码应用于压缩数据以产生码字。响应于通过将压缩应用于写数据而节省的空间量来选择和应用耐久代码。代码字被写入写入地址。

74. 发明申请

US20100218070A1 LENGTHENING LIFE OF A LIMITED LIFE MEMORY 有权
标题翻译：延长有限生命记忆的寿命
公开(公告)号：US20100218070A1
公开(公告)日：2010-08-26
申请号：US12391547
申请日：2009-02-24
申请人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
发明人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
IPC分类号： H03M13/00 , G11C11/00 , G11C7/00 , G06F11/00 , G06F11/16
CPC分类号： G11C13/0069 , G06F11/1012 , G11C13/0002 , G11C2207/104
摘要： A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology). Each one of the storage cells is arbitrarily individually changeable among the at least two levels, and each of the cells is cost-asymmetric. A controller encodes the identical message in the at least first group using the first way or the second way, based on which way incurs a least cost when writing the message into the at least one cell of the at least first group, given current levels of the at least first group.
摘要翻译：相变存储器（PCM）包括存储单元矩阵，至少包括具有至少一个单元的第一组。每个单元包括具有至少第一电阻值和第二电阻值的相变材料，使得第一组可以以至少第一种方式和第二种方式在其中编码相同的消息。所述存储器还包括控制器，所述控制器被配置为在所述至少第一组中对所述第一或第二方式的相同消息进行编码，基于哪种方式，给出所述组的当前级别的最小写入成本量。存储器的另一实施例包括存储单元的矩阵，包括至少一个具有至少一个单元的第一组。每个存储单元具有至少两个级别，使得每个存储单元可以以至少第一种方式和第二种方式在其中编码相同的消息（该单元可以是PCM或另一种技术）。存储单元中的每一个在至少两个级别中可任意地单独变化，并且每个单元是成本不对称的。控制器使用第一种方法或第二种方式在至少第一组中编码相同的消息，基于哪种方式在将消息写入至少第一组的至少一个小区时产生最低成本，给定当前级别至少第一组。

75. 发明申请

US20090006900A1 SYSTEM AND METHOD FOR PROVIDING A HIGH FAULT TOLERANT MEMORY SYSTEM 有权
标题翻译：用于提供高容错记忆体系统的系统和方法
公开(公告)号：US20090006900A1
公开(公告)日：2009-01-01
申请号：US11769936
申请日：2007-06-28
申请人： Luis A. Lastras-Montano , James A. O'Connor , Luiz C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
发明人： Luis A. Lastras-Montano , James A. O'Connor , Luiz C. Alves , William J. Clarke , Timothy J. Dell , Thomas J. Dewkett , Kevin C. Gower
IPC分类号： G06F11/00
CPC分类号： G06F11/1044 , G11C5/04 , G11C29/4401 , G11C29/81 , G11C2029/0409 , G11C2029/0411
摘要： A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.
摘要翻译：一种用于提供高容错存储器系统的系统和方法。该系统包括具有存储器控制器，多个存储器模块和机构的存储器系统。多个存储器模块与存储器控制器和多个存储器件通信。多个存储器件包括用于提供存储器件备用能力的至少一个备用存储器件。该机制用于检测存储器模块中的一个已经失败，可能与另一个存储器模块上的存储器件故障重合。该机制允许存储器系统在存在存储器模块故障和可能的存储器件故障的情况下继续运行不受损害。

76. 发明申请

US20080168329A1 ERROR CONTROL CODING METHODS FOR MEMORIES WITH SUBLINE ACCESSES 失效
标题翻译：具有子网访问记忆的错误控制编码方法
公开(公告)号：US20080168329A1
公开(公告)日：2008-07-10
申请号：US11619929
申请日：2007-01-04
申请人： Junsheng Han , Luis A. Lastras-Montano , Michael R. Trombley
发明人： Junsheng Han , Luis A. Lastras-Montano , Michael R. Trombley
IPC分类号： G06F11/00
CPC分类号： G06F11/1012
摘要： A two-level error control protocol detects errors on the subline level and corrects errors using the codeword for the entire line. This enables a system to read small pieces of coded data and check for errors before accepting them, and in case errors are detected, the whole codeword is read for error correction.
摘要翻译：两级错误控制协议检测子线路上的错误，并使用整个行的代码字纠正错误。这使得系统能够读取小块编码数据并在接受编码数据之前检查错误，并且在检测到错误的情况下，读取整个码字用于纠错。

77. 发明授权

US09881099B2 System, method and computer program product for data transfer management 有权
公开(公告)号：US09881099B2
公开(公告)日：2018-01-30
申请号：US12786072
申请日：2010-05-24
申请人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Danie M. Dreps , Luis A Lastras-Montano , Michael J Shapiro
发明人： Robert H. Bell, Jr. , Louis Bennie Capps, Jr. , Danie M. Dreps , Luis A Lastras-Montano , Michael J Shapiro
IPC分类号： G06F17/30 , G06F12/00 , G06K9/62
CPC分类号： G06F17/30899 , G06F17/30259 , G06K9/6202
摘要： According to one aspect of the present disclosure a method and technique for managing data transfer is disclosed. The method includes comparing, by a processor unit of a data processing system, data to be written to a memory subsystem to a stored data pattern and, responsive to determining that the data matches the stored data pattern, replacing the matching data with a pattern tag corresponding to the matching data pattern. The method also includes transmitting the pattern tag to the memory subsystem.

78. 发明授权

US08990217B2 Lossless compression of high nominal-range data 有权
标题翻译：高标称范围数据的无损压缩
公开(公告)号：US08990217B2
公开(公告)日：2015-03-24
申请号：US13181880
申请日：2011-07-13
申请人： Ashish Jagmohan , Joshua W. Knight , Luis A. Lastras-Montano
发明人： Ashish Jagmohan , Joshua W. Knight , Luis A. Lastras-Montano
IPC分类号： G06F17/30 , H03M7/30
CPC分类号： H03M7/3084 , G06F17/30613 , G06F2212/401
摘要： A method for receiving a data stream that includes data samples, each data sample having one of a plurality of actual values. For each data sample in the data stream, a first index in a dictionary is selected. The dictionary includes indices corresponding to each of the plurality of actual values. The first index corresponds to an actual value of the data sample. A predicted value of the data sample is generated in response to previously received data samples in the data stream and to a prediction algorithm. A second index in the dictionary that corresponds to an actual value in the dictionary that is closest to the value of the predicted value is selected. The difference between the first index and the second index is calculated and compressed. The compressed difference between the first index and the second index is then output. This process is performed for each data sample in the data stream.
摘要翻译：一种用于接收包括数据样本的数据流的方法，每个数据样本具有多个实际值中的一个。对于数据流中的每个数据样本，选择字典中的第一个索引。字典包括与多个实际值中的每一个对应的索引。第一个索引对应于数据样本的实际值。响应于先前接收的数据流中的数据样本和预测算法产生数据样本的预测值。选择字典中对应于字典中与预测值的值最接近的实际值的第二索引。计算并压缩第一个索引和第二个索引之间的差异。然后输出第一索引和第二索引之间的压缩差。对数据流中的每个数据样本执行此过程。

79. 发明授权

US08874846B2 Memory cell presetting for improved memory performance 有权
标题翻译：内存单元预置，以提高内存性能
公开(公告)号：US08874846B2
公开(公告)日：2014-10-28
申请号：US13619451
申请日：2012-09-14
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a method for using a computer system to identify a region in a memory. The region includes a plurality of memory cells characterized by a write performance characteristic that has a first expected value when a write operation changes a current state of the memory cells to a desired state of the memory cells and a second expected value when the write operation changes a specified state of the memory cells to the desired state of the memory cells. The second expected value is closer than the first expected value to a desired value of the write performance characteristic. The plurality of memory cells in the region are set to the specified state, and the data is written into the plurality of memory cells responsive to the setting.
摘要翻译：用于改进性能的存储单元预设，包括使用计算机系统识别存储器中的区域的方法。该区域包括多个存储单元，其特征在于当写入操作将存储单元的当前状态改变到存储单元的期望状态时具有第一期望值的写入性能特性，以及当写入操作改变时第二预期值存储器单元的指定状态到存储器单元的期望状态。第二期望值比第一期望值更接近写入性能特性的期望值。区域中的多个存储单元被设置为指定状态，并且响应于该设置将数据写入多个存储单元。

80. 发明授权

US08806295B2 Mis-correction and no-correction rates for error control 有权
标题翻译：误差校正和无校正率
公开(公告)号：US08806295B2
公开(公告)日：2014-08-12
申请号：US13479855
申请日：2012-05-24
申请人： Ashish Jagmohan , Luis A. Lastras-Montano
发明人： Ashish Jagmohan , Luis A. Lastras-Montano
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F11/1008 , H03M13/1515
摘要： An embodiment is a method for encoding data with an error correction code. The method includes receiving a first number of data symbols by a memory controller, receiving a second number of meta-data sub-symbols, generating a third number of check symbols using an ECC, where the third number includes a difference between a number of symbols in an ECC codeword and the first number and generating a mismatch vector from the check and meta-data sub-symbols, where a number of sub-symbols of the mismatch vector includes the second number. The method also includes generating an adjustment syndrome symbol by multiplying the mismatch vector by a matrix, generating the third number of adjusted check symbols responsive to the adjustment syndrome symbol, and generating a final codeword by concatenating the adjusted check symbols and the data symbols, where the final codeword includes the number of symbols in the ECC codeword.
摘要翻译：实施例是用纠错码对数据进行编码的方法。该方法包括由存储器控制器接收第一数量的数据符号，接收第二数量的元数据子符号，使用ECC生成第三数量的校验符号，其中第三数字包括多个符号之间的差异在ECC码字和第一数字中，并且从校验和元数据子符号生成不匹配向量，其中失配向量的子数目的数目包括第二数目。该方法还包括通过将失配向量乘以矩阵来产生调整校正符号符号，响应于调整校正子符号产生第三数量的经调整的校验符号，以及通过连接调整的校验符号和数据符号来生成最终码字，其中最终码字包括ECC码字中的符号数。

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