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71. 发明授权

US08041912B2 Memory devices with data protection 有权
标题翻译：具有数据保护功能的内存设备
公开(公告)号：US08041912B2
公开(公告)日：2011-10-18
申请号：US11863254
申请日：2007-09-28
申请人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F12/00
CPC分类号： G11C8/20 , G06F21/79 , G11C16/22
摘要： A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.
摘要翻译：存储器件包括存储器阵列，与存储器阵列耦合的状态寄存器，以及与存储器阵列和状态寄存器耦合的安全寄存器。存储器阵列包含被配置为具有独立访问控制的多个存储器块。状态寄存器包括至少一个保护位，指示对应于保护位的存储器块的至少一个相应块的写保护状态。安全寄存器包括至少一个寄存器保护位。寄存器保护位可编程为存储器保护状态，以防止至少状态寄存器的保护位的状态改变。寄存器保护位被配置为保持存储器保护状态，直到存储器件的复位。

72. 发明授权

US07965551B2 Method for metal bit line arrangement 有权
标题翻译：金属位线布置方法
公开(公告)号：US07965551B2
公开(公告)日：2011-06-21
申请号：US11703115
申请日：2007-02-07
申请人： Wen-Chiao Ho , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C7/18 , G11C7/02
摘要： A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is selected as a target memory cell. When the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is a drain metal bit line, and the metal bit line electrically connected to a source is a source metal bit line. Next, a classification of whether the other metal bit lines are charged up when the target memory cell is being read is made. Thereafter, the m metal bit lines are arranged such that charged up metal bit lines are not adjacent to the source metal bit line.
摘要翻译：一种用于金属位线布置的方法被应用于具有存储单元块的虚拟地阵列存储器。每个存储单元块具有存储单元和m个金属位线，其中m是正整数。该方法包括以下步骤。首先，选择一个存储单元作为目标存储单元。当读出目标存储单元时，与目标存储单元的漏极电连接的金属位线是漏极金属位线，与源极电连接的金属位线是源极金属位线。接着，对目标存储单元进行读取时，分类其他金属位线是否被充电。此后，m个金属位线布置成使得带电的金属位线不与源极金属位线相邻。

73. 发明申请

US20100027339A1 PAGE BUFFER AND METHOD OF PROGRAMMING AND READING A MEMORY 有权
标题翻译：页面缓冲区和编程和读取存储器的方法
公开(公告)号：US20100027339A1
公开(公告)日：2010-02-04
申请号：US12182245
申请日：2008-07-30
申请人： Wen-Chiao HO , Chin-Hung CHANG , Kuen-Long CHANG , Chun-Hsiung HUNG
发明人： Wen-Chiao HO , Chin-Hung CHANG , Kuen-Long CHANG , Chun-Hsiung HUNG
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C2211/5621 , G11C2211/5646 , G11C2216/14
摘要： A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell.
摘要翻译：提供了一种页面缓冲器和编程和读取存储器的方法。页面缓冲器包括第一锁存器，第二锁存器，数据改变单元和程序控制单元。第一锁存器包括用于加载下页和上页的数据的第一终端。第二锁存器包括用于存储来自第一锁存器的下页数据和上页数据的第一终端。数据改变单元耦合到第一锁存器的第二端子，用于将第一锁存器的第二端子的电压改变到低电平。程序控制单元耦合到第二锁存器和单元的第一端子，并且由第一锁存器的第一端子的电压控制，以分别将下页数据和上部页面的数据编程到目标单元。

74. 发明授权

US07652512B2 Clock synchronizing circuit 有权
标题翻译：时钟同步电路
公开(公告)号：US07652512B2
公开(公告)日：2010-01-26
申请号：US12027285
申请日：2008-02-07
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , H03K5/06 , H03K2005/00195
摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.
摘要翻译：提供了应用在SMD块中的时钟同步电路。时钟同步电路包括多个时钟同步单元级。时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生用于触发前级延迟单元各级的输出时钟的短脉冲。

75. 发明申请

US20100007377A1 METHOD AND SYSTEM FOR A SERIAL PERIPHERAL INTERFACE 有权
标题翻译：串行外围接口的方法和系统
公开(公告)号：US20100007377A1
公开(公告)日：2010-01-14
申请号：US12564789
申请日：2009-09-22
申请人： Chun-Hsiung Hing , Kuen-Long Chang , Chia-He Liu
发明人： Chun-Hsiung Hing , Kuen-Long Chang , Chia-He Liu
IPC分类号： H03K19/173
CPC分类号： G11C7/1045 , G11C7/1072 , G11C7/22
摘要： An integrated circuit device includes a serial peripheral interface adapted for receiving a first command supporting an address of a first configuration, wherein the serial peripheral interface supports an address of a second configuration upon receipt of a second command, the second configuration being different from the first configuration. In a specific embodiment, the first and the second configurations are different in address length. In another embodiment, a second address cooperated with the second command has a first part and a second part, the second part comprising a plurality of byte addresses, each of the byte addresses being associated with a corresponding byte of data. In another embodiment, integrated circuit device also includes a mode logic circuit for controlling operations of the first command and the second command. Various other embodiments are also described.
摘要翻译：集成电路装置包括适于接收支持第一配置的地址的第一命令的串行外围接口，其中，所述串行外设接口在接收到第二命令时支持第二配置的地址，所述第二配置不同于所述第一配置组态。在具体实施例中，第一和第二配置的地址长度不同。在另一个实施例中，与第二命令协作的第二地址具有第一部分和第二部分，第二部分包括多个字节地址，每个字节地址与对应的数据字节相关联。在另一实施例中，集成电路装置还包括用于控制第一命令和第二命令的操作的模式逻辑电路。还描述了各种其它实施例。

76. 发明授权

US07639533B2 Multi-level memory cell programming methods 有权
标题翻译：多级存储单元编程方法
公开(公告)号：US07639533B2
公开(公告)日：2009-12-29
申请号：US12028405
申请日：2008-02-08
申请人： Chin-Hung Chang , Wen-Chiao Ho , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Chin-Hung Chang , Wen-Chiao Ho , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C11/03
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： A method for programming a plurality of multi-level memory cells described herein includes iteratively changing a bias voltage applied to a first memory cell to program the first memory cell to a first threshold state and detecting when the first cell reaches a predetermined threshold voltage. The bias voltage applied to the first memory cell upon reaching the predetermined threshold voltage is recorded. A second memory cell is programmed to a second threshold state by applying an initial bias voltage to the second memory cell which is function of the recorded bias voltage.
摘要翻译：用于编程本文所述的多个多电平存储器单元的方法包括迭代地改变施加到第一存储器单元的偏置电压，以将第一存储器单元编程为第一阈值状态，以及检测第一单元何时达到预定阈值电压。记录在达到预定阈值电压时施加到第一存储单元的偏置电压。通过对作为记录的偏置电压的函数的第二存储器单元施加初始偏置电压将第二存储单元编程为第二阈值状态。

77. 发明授权

US07626867B2 Method for accessing memory by way of step-increasing threshold voltage 有权
标题翻译：通过增加阈值电压来访问存储器的方法
公开(公告)号：US07626867B2
公开(公告)日：2009-12-01
申请号：US12174115
申请日：2008-07-16
申请人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
发明人： Chun-Hsiung Hung , Wen-Chiao Ho , Kuen-Long Chang
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C11/5671
摘要： A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively, wherein each of the 2n level corresponds to a storage status of n bits, and most significant bits of the storage statuses which level 0 to level 2n/2−1 correspond to are different from most significant bits of the storage statuses which level 2n/2 to level 2n−1 correspond to. Next, a target data is divided into n portions and the divided target data is written into n temporary memories respectively. Then, n bits of the target data are written into the multi-level cell. Each of the n bits data is collected from each of the n temporary memories.
摘要翻译：提供了访问存储器的方法。存储器包括许多多级单元，每个单元具有至少一个能存储2n位的存储器，n是正整数。访问存储器的方法包括以下步骤：首先，将存储器的阈值电压分别定义为2n级，其中2n级中的每一级对应于n位的存储状态，存储状态的最高有效位为0级等级2n / 2-1对应于不同于2n / 2到2n-1级对应的存储状态的最高有效位。接下来，目标数据被分成n个部分，分割的目标数据被分别写入n个临时存储器。然后，将目标数据的n位写入多级单元。从n个临时存储器中的每一个收集n位数据中的每一个。

78. 发明授权

US07613049B2 Method and system for a serial peripheral interface 有权
标题翻译：串行外设接口的方法和系统
公开(公告)号：US07613049B2
公开(公告)日：2009-11-03
申请号：US11969856
申请日：2008-01-04
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Chia-He Liu
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Chia-He Liu
IPC分类号： G11C7/10
CPC分类号： G11C7/1045 , G11C7/1072 , G11C7/22
摘要： A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.
摘要翻译：一种用于在包括串行外设接口存储器件的集成电路中读取的双I / O数据的方法。在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。在一个实施例中，配置寄存器包括等待周期计数。该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

79. 发明申请

US20090059668A1 Virtual ground array memory and programming method thereof 有权
公开(公告)号：US20090059668A1
公开(公告)日：2009-03-05
申请号：US11892979
申请日：2007-08-29
申请人： Chin-Hung Chang , Wen-Chiao Ho , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Chin-Hung Chang , Wen-Chiao Ho , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0491
摘要： A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails.

80. 发明授权

US07499335B2 Non-volatile memory with improved erasing operation 有权
标题翻译：非易失性存储器，具有改进的擦除操作
公开(公告)号：US07499335B2
公开(公告)日：2009-03-03
申请号：US11703916
申请日：2007-02-07
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/107 , G11C16/16 , G11C16/3459 , G11C2211/5621
摘要： A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.
摘要翻译：在具有多个存储单元的非易失性存储器中公开了一种用于执行擦除操作的方法。至少一个存储器单元被编程为在编程之前具有第一区域中的阈值电压电平，并且在编程之后，存储器单元在第二区域中具有阈值电压电平，其中第二区域的阈值电压高于第一区域。擦除操作实现了可以将负电荷载流子或电子注入到存储单元中的存储器位的编程，而不是使用将热空穴注入存储单元的常规技术。这可以避免热空穴注入引起的室温漂移和电荷损失。

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