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71. 发明授权

US08803294B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08803294B2
公开(公告)日：2014-08-12
申请号：US13529602
申请日：2012-06-21
申请人： Takeyoshi Masuda , Shin Harada , Keiji Wada , Toru Hiyoshi
发明人： Takeyoshi Masuda , Shin Harada , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/24
CPC分类号： H01L29/7802 , H01L21/049 , H01L21/3065 , H01L29/045 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7397 , H01L29/7813
摘要： A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.
摘要翻译：衬底具有由具有多晶型4H的六方晶单晶结构的半导体制成的表面。基板的表面通过交替地提供具有（0-33-8）的平面取向的第一平面和连接到第一平面并具有不同于第一平面的平面取向的平面取向的第二平面来构造。栅极绝缘膜设置在基板的表面上。在栅极绝缘膜上设置栅电极。

72. 发明授权

US08686435B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US08686435B2
公开(公告)日：2014-04-01
申请号：US13434233
申请日：2012-03-29
申请人： Takeyoshi Masuda , Toru Hiyoshi , Keiji Wada
发明人： Takeyoshi Masuda , Toru Hiyoshi , Keiji Wada
IPC分类号： H01L21/336 , H01L29/04 , H01L29/12 , H01L29/78
CPC分类号： H01L21/28 , H01L21/0475 , H01L21/049 , H01L21/306 , H01L21/3065 , H01L29/045 , H01L29/0623 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7813
摘要： A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm−3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.
摘要翻译：在基板的主表面上外延形成碳化硅层。碳化硅层设置有具有相对于主表面倾斜的侧壁的沟槽。侧壁相对于{0001}面具有不小于50°且不超过65°的偏离角。栅极绝缘膜设置在碳化硅层的侧壁上。碳化硅层包括：具有第一导电类型且面对栅电极的主体区域，栅极绝缘膜介于其间; 以及一对由身体区域彼此隔开并具有第二导电类型的区域。体区的杂质密度为5×1016 cm -3以上。这允许在抑制信道移动性的降低的同时增加设置阈值电压的自由度。

73. 发明授权

US08610132B2 Semiconductor device and method for manufacturing semiconductor device 有权
公开(公告)号：US08610132B2
公开(公告)日：2013-12-17
申请号：US13613801
申请日：2012-09-13
申请人： Takeyoshi Masuda , Keiji Wada , Toru Hiyoshi
发明人： Takeyoshi Masuda , Keiji Wada , Toru Hiyoshi
IPC分类号： H01L29/78
CPC分类号： H01L21/265 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/42372 , H01L29/4238 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection.

74. 发明授权

US08610131B2 Silicon carbide insulated-gate bipolar transistor 有权
标题翻译：碳化硅绝缘栅双极晶体管
公开(公告)号：US08610131B2
公开(公告)日：2013-12-17
申请号：US13435863
申请日：2012-03-30
申请人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
IPC分类号： H01L29/15
CPC分类号： H01L29/7397 , H01L21/0475 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/4236 , H01L29/66068
摘要： An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm−3 or more.
摘要翻译： IGBT包括设置在碳化硅半导体层中的沟槽，设置在碳化硅半导体层中的第一导电类型的主体区域以及至少覆盖该沟槽的侧壁表面的绝缘膜，槽的侧壁表面为相对于{0001}面具有偏离角度为50°以上且65°以下的表面，所述凹槽的侧壁表面包括所述主体区域的表面，所述绝缘膜至少与所述表面接触在所述槽的侧壁面的所述主体区域中，所述体区的第一导电型杂质浓度为5×10 16 cm -3以上。

75. 发明申请

US20130040445A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130040445A1
公开(公告)日：2013-02-14
申请号：US13583564
申请日：2011-11-07
申请人： Ryosuke Kubota , Keiji Wada , Takeyoshi Masuda , Hiromu Shiomi
发明人： Ryosuke Kubota , Keiji Wada , Takeyoshi Masuda , Hiromu Shiomi
IPC分类号： H01L21/265
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/268 , H01L29/1608 , H01L29/66068
摘要： A silicon carbide substrate having a surface is prepared. An impurity region is formed by implanting ions from the surface into the silicon carbide substrate. Annealing for activating the impurity region is performed. The annealing includes the step of applying first laser light having a first wavelength to the surface of the silicon carbide substrate, and the step of applying second laser light having a second wavelength to the surface of the silicon carbide substrate. The silicon carbide substrate has first and second extinction coefficients at the first and second wavelengths, respectively. A ratio of the first extinction coefficient to the first wavelength is higher than 5×105/m. A ratio of the second extinction coefficient to the second wavelength is lower than 5×105/m. Consequently, damage to the surface of the silicon carbide substrate during laser annealing can be reduced.
摘要翻译：制备具有表面的碳化硅衬底。通过从表面注入离子到碳化硅衬底中形成杂质区。执行用于激活杂质区域的退火。退火包括将具有第一波长的第一激光施加到碳化硅衬底的表面的步骤，以及将具有第二波长的第二激光施加到碳化硅衬底的表面的步骤。碳化硅衬底分别在第一和第二波长处具有第一和第二消光系数。第一消光系数与第一波长的比率高于5×10 5 / m。第二消光系数与第二波长的比率低于5×10 5 / m。因此，可以减少在激光退火期间对碳化硅衬底的表面的损坏。

76. 发明申请

US20120305943A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20120305943A1
公开(公告)日：2012-12-06
申请号：US13485423
申请日：2012-05-31
申请人： Misako HONAGA , Takeyoshi MASUDA , Keiji WADA , Toru HIYOSHI
发明人： Misako HONAGA , Takeyoshi MASUDA , Keiji WADA , Toru HIYOSHI
IPC分类号： H01L29/161 , H01L21/334
CPC分类号： H01L29/7802 , H01L29/0878 , H01L29/1095 , H01L29/66068
摘要： A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j−N2j>N1d and N2j
摘要翻译：漂移层具有电流流动的厚度方向，并具有用于第一导电类型的杂质浓度N1d。身体区域设置在漂移层的一部分上，具有由栅电极切换的通道，具有用于第一导电类型的杂质浓度N1b，并且具有大于杂质的第二导电类型的杂质浓度N2b 浓度N1b。 JFET区域与漂移层上的体区附近配置，对于第一导电类型具有杂质浓度N1j，并且对于第二导电类型的杂质浓度N2j小于杂质浓度N1j。 N1j-N2j> N1d和N2j

77. 发明申请

US20120286291A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20120286291A1
公开(公告)日：2012-11-15
申请号：US13520702
申请日：2011-03-04
申请人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
发明人： Toru Hiyoshi , Takeyoshi Masuda , Keiji Wada
IPC分类号： H01L29/161 , H01L21/20
CPC分类号： H01L29/7802 , H01L21/049 , H01L21/8213 , H01L29/045 , H01L29/1608 , H01L29/513 , H01L29/518 , H01L29/6606 , H01L29/66068 , H01L29/94
摘要： A silicon carbide semiconductor device having excellent electrical characteristics including channel mobility and a method for manufacturing the same are provided. The method for manufacturing a silicon carbide semiconductor device includes: an epitaxial layer forming step of preparing a semiconductor film of silicon carbide; a gate insulating film forming step of forming an oxide film on a surface of the semiconductor film; a nitrogen annealing step of performing heat treatment on the semiconductor film on which the oxide film is formed, in a nitrogen-containing atmosphere; and a post heat treatment step of performing, after the nitrogen annealing step, post heat treatment on the semiconductor film on which the oxide film is formed, in an atmosphere containing an inert gas. The heat treatment temperature in the post heat treatment step is higher than that in the nitrogen annealing step and lower than a melting point of the oxide film.
摘要翻译：提供一种具有优异的包括沟道迁移率的电特性的碳化硅半导体器件及其制造方法。制造碳化硅半导体器件的方法包括：制备碳化硅半导体膜的外延层形成步骤; 在所述半导体膜的表面上形成氧化膜的栅极绝缘膜形成工序; 在含氮气氛中对形成有氧化膜的半导体膜进行热处理的氮退火工序; 以及后处理工序，在氮退火工序后，在含有惰性气体的气氛中对形成有氧化膜的半导体膜进行后热处理。后热处理工序中的热处理温度高于氮退火工序中的热处理温度，低于氧化膜的熔点。

78. 发明申请

US20120248462A1 IGBT 有权
公开(公告)号：US20120248462A1
公开(公告)日：2012-10-04
申请号：US13435863
申请日：2012-03-30
申请人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
发明人： Keiji Wada , Takeyoshi Masuda , Misako Honaga , Toru Hiyoshi
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L21/0475 , H01L21/049 , H01L29/045 , H01L29/1608 , H01L29/4236 , H01L29/66068
摘要： An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm−3 or more.
摘要翻译： IGBT包括设置在碳化硅半导体层中的沟槽，设置在碳化硅半导体层中的第一导电类型的主体区域以及至少覆盖该沟槽的侧壁表面的绝缘膜，槽的侧壁表面为相对于{0001}面具有偏离角度为50°以上且65°以下的表面，所述凹槽的侧壁表面包括所述主体区域的表面，所述绝缘膜至少与所述表面接触在所述槽的侧壁面的所述主体区域中，所述体区的第一导电型杂质浓度为5×10 16 cm -3以上。

79. 发明申请

US20120018743A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120018743A1
公开(公告)日：2012-01-26
申请号：US13190001
申请日：2011-07-25
申请人： Toru Hiyoshi , Keiji Wada , Takeyoshi Masuda , Hiromu Shiomi
发明人： Toru Hiyoshi , Keiji Wada , Takeyoshi Masuda , Hiromu Shiomi
IPC分类号： H01L29/772
CPC分类号： H01L29/7802 , H01L21/049 , H01L29/045 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7395
摘要： A MOSFET includes a silicon carbide substrate including a main surface having an off angle of not less than 50° and not more than 65° with respect to a {0001} plane, a buffer layer and a drift layer formed on the main surface, a gate oxide film formed on and in contact with the drift layer, and a p type body region of a p conductivity type formed in the drift layer to include a region in contact with the gate oxide film. The p type body region has a p type impurity density of not less than 5×1016 cm−3.
摘要翻译： MOSFET包括碳化硅衬底，其包括相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面，形成在主表面上的缓冲层和漂移层，形成在漂移层上并与漂移层接触的栅氧化膜，以及在漂移层中形成的ap导电型的p型体区域，以包括与栅氧化膜接触的区域。 p型体区的p型杂质密度为5×1016cm-3以上。

80. 发明授权

US6126080A Air conditioner 失效
标题翻译：冷气机
公开(公告)号：US6126080A
公开(公告)日：2000-10-03
申请号：US948272
申请日：1997-10-09
申请人： Keiji Wada
发明人： Keiji Wada
IPC分类号： F24F11/00 , G05D23/00
CPC分类号： F24F11/006 , F24F2011/0067
摘要： In an air conditioner including an outdoor unit and plural indoor units, the outdoor unit is provided with an indoor unit operation setting mechanism for setting the driving operation of the indoor units, and the indoor unit operation setting mechanism is provided with operation control parameter changing means for changing the storage content of storage means of each indoor unit and/or master/slave setting means for automatically performing the master/slave setting operation of the indoor units.
摘要翻译：在具有室外机和多台室内机的空调机中，室外机设置有室内机操作设定机构，用于设定室内机的驾驶操作，室内机操作设定机构具备操作控制参数改变单元用于改变每个室内单元和/或主/从设置装置的存储装置的存储内容，用于自动执行室内单元的主/从设置操作。

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