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71. 发明授权

US07986565B2 Method of erasing data in flash memory device 失效
标题翻译：擦除闪存设备中数据的方法
公开(公告)号：US07986565B2
公开(公告)日：2011-07-26
申请号：US12458502
申请日：2009-07-14
申请人： Jin-Young Chun , Jae-Yong Jeong
发明人： Jin-Young Chun , Jae-Yong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage.
摘要翻译：一种擦除闪速存储器件中的数据的方法，包括使用第一擦除电压擦除至少一个闪存单元中的数据; 检测所述至少一个闪存单元是否具有小于第一电压的阈值电压; 如果所述检测步骤检测到所述阈值电压小于所述第一电压，则使用大于所述第一电压的第二电压改变所述至少一个闪存单元的阈值电压来对所述至少一个闪存单元进行编程; 如果所述检测步骤检测到所述阈值电压大于所述第一电压，则保持所述至少一个闪存单元的阈值电压; 以及使用第一验证电压验证所述至少一个闪存单元。

72. 发明授权

US07821837B2 Reprogrammable nonvolatile memory devices and methods 失效
标题翻译：可重复编程的非易失性存储器件和方法
公开(公告)号：US07821837B2
公开(公告)日：2010-10-26
申请号：US12466679
申请日：2009-05-15
申请人： Jin-Young Chun , Jae-Yong Jeong
发明人： Jin-Young Chun , Jae-Yong Jeong
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/26 , G11C16/3459
摘要： A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.
摘要翻译：非易失性存储器件包括：命令解码器，被配置为响应于读/写命令产生读/写标志信号，并且响应于重编程命令产生再编程标志信号;以及读/写电路，被配置为控制读/ 在存储单元阵列中进行写操作。该装置还包括读/写控制器，其被配置为使得读/写电路响应于从命令解码器提供的读/写标志信号执行读/写操作;以及重新编程控制器，其被配置为使读/ 控制器响应于重新编程标志信号执行重新编程操作。重新编程存储器件的方法包括：确定存储器件是否处于忙状态，如果存储器件处于忙状态，则延迟重新编程操作，并且当存储器件已经从忙时转为待机状态时执行重新编程操作州。

73. 发明授权

US07782680B2 Flash memory device having a verify data buffer capable of being employed as a program data buffer, and a method thereof 有权
标题翻译：具有能够被用作程序数据缓冲器的验证数据缓冲器的闪速存储器件及其方法
公开(公告)号：US07782680B2
公开(公告)日：2010-08-24
申请号：US12003589
申请日：2007-12-28
申请人： Kee-ho Jung , Jae-yong Jeong , Chi-weon Yoon
发明人： Kee-ho Jung , Jae-yong Jeong , Chi-weon Yoon
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.
摘要翻译：闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中，验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。

74. 发明申请

US20100118613A1 Method of erasing data in flash memory device 失效
标题翻译：擦除闪存设备中数据的方法
公开(公告)号：US20100118613A1
公开(公告)日：2010-05-13
申请号：US12458502
申请日：2009-07-14
申请人： Jin-young Chun , Jae-yong Jeong
发明人： Jin-young Chun , Jae-yong Jeong
IPC分类号： G11C16/14 , G11C16/04 , G11C29/00 , G11C16/06
CPC分类号： G11C16/16 , G11C16/344 , G11C16/3445
摘要： A method of erasing data in a flash memory device, including erasing data in at least one flash memory cell using a first erase voltage; detecting whether the at least one flash memory cell has a threshold voltage less than a first voltage; programming the at least one flash memory cell by varying the threshold voltage of the at least one flash memory cell using a second voltage that is greater than the first voltage if the detecting step detects the threshold voltage is less than the first voltage; maintaining the threshold voltage of the at least one flash memory cell if the detecting step detects the threshold voltage is greater than the first voltage; and verifying the at least one flash memory cell using a first verification voltage.
摘要翻译：一种擦除闪速存储器件中的数据的方法，包括使用第一擦除电压擦除至少一个闪存单元中的数据; 检测所述至少一个闪存单元是否具有小于第一电压的阈值电压; 如果所述检测步骤检测到所述阈值电压小于所述第一电压，则使用大于所述第一电压的第二电压改变所述至少一个闪存单元的阈值电压来对所述至少一个闪存单元进行编程; 如果所述检测步骤检测到所述阈值电压大于所述第一电压，则保持所述至少一个闪存单元的阈值电压; 以及使用第一验证电压验证所述至少一个闪存单元。

75. 发明申请

US20100054037A1 FLASH MEMORY DEVICE WITH MULTI LEVEL CELL AND BURST ACCESS METHOD THEREIN 失效
标题翻译：具有多级电池的闪存存储器件及其触发方式
公开(公告)号：US20100054037A1
公开(公告)日：2010-03-04
申请号：US12615374
申请日：2009-11-10
申请人： JUNG-WOO LEE , JAE-YONG JEONG
发明人： JUNG-WOO LEE , JAE-YONG JEONG
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C11/5628 , G11C2211/5633
摘要： A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.
摘要翻译：一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字，重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。

76. 发明授权

US07668015B2 Nonvolatile memory devices capable of reducing data programming time and methods of driving the same 失效
标题翻译：能够减少数据编程时间的非易失性存储器件及其驱动方法
公开(公告)号：US07668015B2
公开(公告)日：2010-02-23
申请号：US12005366
申请日：2007-12-27
申请人： Jae-phil Kong , Heung-soo Lim , Jae-yong Jeong , Chi-weon Yoon
发明人： Jae-phil Kong , Heung-soo Lim , Jae-yong Jeong , Chi-weon Yoon
IPC分类号： G11C16/04
CPC分类号： G11C11/5628
摘要： In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.
摘要翻译：在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。搜索到的数据位被编程为响应于同时编程的位的数量。对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

77. 发明授权

US07643340B2 Method and apparatus for programming multi level cell flash memory device 失效
标题翻译：用于编程多级单元闪存器件的方法和装置
公开(公告)号：US07643340B2
公开(公告)日：2010-01-05
申请号：US11946228
申请日：2007-11-28
申请人： Jae-Phil Kong , Jae-Yong Jeong
发明人： Jae-Phil Kong , Jae-Yong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C11/5628
摘要： A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.
摘要翻译：一种在多级闪速存储器件中对所选单元进行编程的方法包括：确定是否编程所选存储单元的高位或低位，检测存储在所选存储单元中的两位数据的当前逻辑状态，确定上位或下位的目标逻辑状态，产生用于将上位或下位编程为目标逻辑状态的编程电压和验证电压，以及将编程电压和验证电压施加到连接到所选择的字线的字线记忆单元

78. 发明授权

US07602650B2 Flash memory device and method for programming multi-level cells in the same 失效
标题翻译：闪存设备和方法用于编程多级单元格
公开(公告)号：US07602650B2
公开(公告)日：2009-10-13
申请号：US11847388
申请日：2007-08-30
申请人： Kee-Ho Jung , Jae-Yong Jeong , Chi-Weon Yoon
发明人： Kee-Ho Jung , Jae-Yong Jeong , Chi-Weon Yoon
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a threshold voltage corresponding to the first data state, and verifying results of the successive programming.
摘要翻译：在一个方面，提供了一种用于闪存器件的程序方法，其包括多个存储器单元，每个存储器单元以多个数据状态中的一个被编程。该方面的程序方法包括以第一数据状态编程所选择的存储单元，验证编程结果，以对应于低于对应于阈值电压的阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选存储单元第一数据状态，以及验证连续编程的结果。

79. 发明申请

US20090225603A1 Reprogrammable Nonvolatile Memory Devices and Methods 失效
标题翻译：可重复编程的非易失性存储器件和方法
公开(公告)号：US20090225603A1
公开(公告)日：2009-09-10
申请号：US12466679
申请日：2009-05-15
申请人： JIN-YOUNG CHUN , JAE-YONG JEONG
发明人： JIN-YOUNG CHUN , JAE-YONG JEONG
IPC分类号： G11C16/04 , G11C7/00 , G11C8/10
CPC分类号： G11C16/12 , G11C16/26 , G11C16/3459
摘要： A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.
摘要翻译：非易失性存储器件包括：命令解码器，被配置为响应于读/写命令产生读/写标志信号，并且响应于重编程命令产生再编程标志信号;以及读/写电路，被配置为控制读/ 在存储单元阵列中进行写操作。该装置还包括读/写控制器，其被配置为使得读/写电路响应于从命令解码器提供的读/写标志信号执行读/写操作;以及重新编程控制器，其被配置为使读/ 控制器响应于重新编程标志信号执行重新编程操作。重新编程存储器件的方法包括：确定存储器件是否处于忙状态，如果存储器件处于忙状态，则延迟重新编程操作，并且当存储器件已经从忙时转为待机状态时执行重新编程操作州。

80. 发明申请

US20090003056A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其编程方法
公开(公告)号：US20090003056A1
公开(公告)日：2009-01-01
申请号：US12129820
申请日：2008-05-30
申请人： Jin-Young CHUN , Jae-Yong JEONG , Chi-Weon YOON
发明人： Jin-Young CHUN , Jae-Yong JEONG , Chi-Weon YOON
IPC分类号： G11C16/06 , G11C16/00
CPC分类号： G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.
摘要翻译：公开了一种非易失性存储器件的非易失性存储器件和编程方法。非易失性存储器件的编程方法包括对存储器单元执行第一编程操作，在第一编程操作之后从存储单元检索原始数据，并参考原始数据和第二验证电压进行第二编程操作比第一编程操作的第一验证电压。

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