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71. 发明申请

US20080137435A1 Flash memory devices that support incremental step-pulse programming using nonuniform verify time intervals 有权
标题翻译：使用非均匀验证时间间隔支持增量式步进脉冲编程的闪存设备
公开(公告)号：US20080137435A1
公开(公告)日：2008-06-12
申请号：US12031422
申请日：2008-02-14
申请人： Soo-Han Kim , Jae-Yong Jeong
发明人： Soo-Han Kim , Jae-Yong Jeong
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g., ΔV1) and then, in response to verifying that at least one of the memory cells coupled to the selected word line is a passed memory cell, driving the selected word line with a second stair step sequence of program voltages having a second step height (e.g., ΔV2) lower than the first step height.
摘要翻译：非易失性存储器件支持编程和验证操作，以改善程序存储单元内的阈值电压分布。一旦将经历编程的多个存储器单元中的至少一个已经被验证为“传递”的存储器单元，则通过减小编程电压步长的大小并增加验证操作的持续时间来实现这种改进。非易失性存储器件包括非易失性存储器单元的阵列和电耦合到非易失性存储单元阵列的控制电路。控制电路被配置为通过以具有第一台阶高度（例如，DeltaV 1）的编程电压的第一阶梯顺序驱动阵列中的选定字线来执行多个存储器编程操作（P），然后响应于验证耦合到所选择的字线的存储器单元中的至少一个是经过的存储单元，用具有低于第一个字线的第二阶梯高度（例如，DeltaV 2）的编程电压的第二阶梯顺序驱动所选择的字线步高。

72. 发明授权

US07298654B2 Non-volatile memory device and associated method of erasure 失效
标题翻译：非易失性存储器件及相关的擦除方法
公开(公告)号：US07298654B2
公开(公告)日：2007-11-20
申请号：US11133234
申请日：2005-05-20
申请人： Jae-Yong Jeong , Young-Ho Lim
发明人： Jae-Yong Jeong , Young-Ho Lim
IPC分类号： G11C11/34
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/3404 , G11C16/344 , G11C16/3445
摘要： Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.
摘要翻译：公开了一种非易失性存储器件和擦除非易失性存储器件的方法。同时将擦除电压施加到包含在非易失性存储器件中的多个扇区。然后，针对多个扇区中的每一个依次执行擦除验证，并将擦除确认的结果存储在多个通过信息寄存器中。根据存储在通过信息寄存器中的结果，同时重新擦除未成功擦除的扇区，然后顺序重新验证，直到在非易失性存储器件中不存在这样的“故障扇区”为止。在从非易失性存储器件消除“故障扇区”时，对多个扇区中的每一个依次执行后编程操作。

73. 发明授权

US07286413B2 Non-volatile memory device and method of programming same 失效
标题翻译：非易失性存储器件和编程方法相同
公开(公告)号：US07286413B2
公开(公告)日：2007-10-23
申请号：US11257074
申请日：2005-10-25
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/24
摘要： Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.
摘要翻译：公开了一种非易失性存储器件及其编程方法。该方法包括在多个程序循环期间将字线电压，位线电压和体电压施加到存储器单元。在当前程序循环期间位线电压下降到低于第一预定检测电压或体电压变得高于第二预定检测电压的情况下，在当前编程环路中使用相同的字线电压，并在下一个程序循环当前程序循环。否则，在下一个编程循环之前，字线电压增加预定量。

74. 发明申请

US20070183216A1 Reprogrammable nonvolatile memory devices and methods 失效
标题翻译：可重复编程的非易失性存储器件和方法
公开(公告)号：US20070183216A1
公开(公告)日：2007-08-09
申请号：US11634058
申请日：2006-12-05
申请人： Jin-Young Chun , Jae-Yong Jeong
发明人： Jin-Young Chun , Jae-Yong Jeong
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C16/12 , G11C16/26 , G11C16/3459
摘要： A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.
摘要翻译：非易失性存储器件包括：命令解码器，被配置为响应于读/写命令产生读/写标志信号，并且响应于重编程命令产生再编程标志信号;以及读/写电路，被配置为控制读/ 在存储单元阵列中进行写操作。该装置还包括读/写控制器，其被配置为使得读/写电路响应于从命令解码器提供的读/写标志信号执行读/写操作;以及重新编程控制器，其被配置为使读/ 控制器响应于重新编程标志信号执行重新编程操作。重新编程存储器件的方法包括：确定存储器件是否处于忙状态，如果存储器件处于忙状态，则延迟重新编程操作，并且当存储器件已经从忙时转为待机状态时执行重新编程操作州。

75. 发明授权

US07239554B2 Nonvolatile memory device and method of improving programming characteristic 失效
标题翻译：非易失性存储器件和改进编程特性的方法
公开(公告)号：US07239554B2
公开(公告)日：2007-07-03
申请号：US11133286
申请日：2005-05-20
申请人： Jae-yong Jeong
发明人： Jae-yong Jeong
IPC分类号： G11C16/04 , G11C16/06 , G11C7/06 , G11C5/14 , G11C7/02
CPC分类号： G11C16/102 , G11C16/30
摘要： A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage is less than the detection voltage, a second pump becomes active.
摘要翻译：一种编程非易失性存储器件的方法包括激活第一泵以产生位线电压，并且在体电压达到目标电压之后，检测位线电压是否小于检测电压。当位线电压小于检测电压时，第二个泵变为有效。

76. 发明申请

US20070109873A1 Non-volatile memory device having controlled bulk voltage and method of programming same 审中-公开
标题翻译：具有受控体积电压的非易失性存储器件及其编程方法
公开(公告)号：US20070109873A1
公开(公告)日：2007-05-17
申请号：US11649815
申请日：2007-01-05
申请人： Jae-Yong Jeong , Heung-Soo Lim
发明人： Jae-Yong Jeong , Heung-Soo Lim
IPC分类号： G11C7/10
CPC分类号： G11C16/30 , G11C16/10
摘要： Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.
摘要翻译：公开了一种非易失性存储器件及其编程方法。通过将字线电压，位线电压和体电压施加到器件内的存储器单元来编程非易失性存储器件。在器件的编程操作期间，体电压由第一泵产生。然而，在体电压超过预定检测电压的情况下，第二泵进一步被激活以便降低体电压。

77. 发明授权

US07149528B2 Method for controlling overload in digital mobile communication system 失效
标题翻译：数字移动通信系统过载控制方法
公开(公告)号：US07149528B2
公开(公告)日：2006-12-12
申请号：US09767563
申请日：2001-01-23
申请人： Young-Il Lim , Jae-Yong Jeong , Myoung-Ki Seol
发明人： Young-Il Lim , Jae-Yong Jeong , Myoung-Ki Seol
IPC分类号： H04Q7/20
CPC分类号： H04W24/08 , H04M3/365
摘要： A method for controlling an overload of a digital mobile communication system. The digital mobile communication system has a base transceiver station and a base station controller each of which has a database. The method for controlling the overload includes the steps of: a) initializing threshold values stored on the database as a predetermined value; b) monitoring each of utility rates of a control processor resource and a call resource; c) comparing the utility rates of the control processor resource and the call resource with the threshold values respectively, thereby obtaining overload grades of the control processor resource and the call resource; d) comparing the overload grade of the control processor resource with the overload grade of the call resource, thereby selecting one of the control processor resource and the call resource as a resource to be controlled, which has a higher overload grade; e) determining whether an overload occurs in the resource to be controlled; and f) if the overload occurs in the resource to be controlled, informing a base station manager of an occurrence in the resource to be controlled.
摘要翻译：一种用于控制数字移动通信系统的过载的方法。数字移动通信系统具有基站收发台和基站控制器，每个基站具有数据库。用于控制过载的方法包括以下步骤：a）将存储在数据库上的阈值初始化为预定值; b）监控控制处理器资源和呼叫资源的每个利用率; c）分别将控制处理器资源和呼叫资源的利用率与阈值进行比较，从而获得控制处理器资源和呼叫资源的过载等级; d）将控制处理器资源的过载等级与呼叫资源的过载等级进行比较，从而选择控制处理器资源和呼叫资源之一作为要控制的资源，具有较高的过载等级; e）确定在要控制的资源中是否发生过载; 以及f）如果在要控制的资源中发生过载，则向基站管理员通知要控制的资源中的发生。

78. 发明申请

US20060087888A1 Nonvolatile memory device and method of programming same 有权
标题翻译：非易失性存储器件及其编程方法
公开(公告)号：US20060087888A1
公开(公告)日：2006-04-27
申请号：US11106640
申请日：2005-04-15
申请人： Jae-Yong Jeong
发明人： Jae-Yong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/102
摘要： A nonvolatile memory device and method of programming the device are disclosed. The nonvolatile memory device is adapted to interrupt or resume a programming operation for a memory cell of the device in response to variation in a programming voltage being supplied to the memory cell. The programming operation is typically interrupted or resumed in response to signals generated by a program controller and/or a detector monitoring the programming voltage.
摘要翻译：公开了一种非易失性存储器件及其编程方法。非易失性存储器件适于响应于提供给存储器单元的编程电压的变化而中断或恢复器件的存储器单元的编程操作。响应于由程序控制器和/或监视编程电压的检测器产生的信号，编程操作通常被中断或恢复。

79. 发明申请

US20060056237A1 Non-volatile memory device with scanning circuit and method 失效
标题翻译：具有扫描电路和方法的非易失性存储器件
公开(公告)号：US20060056237A1
公开(公告)日：2006-03-16
申请号：US11181163
申请日：2005-07-13
申请人： Jae-Yong Jeong
发明人： Jae-Yong Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/32
摘要： I describe and claim an accelerated bit scanning nonvolatile memory device and method. A nonvolatile memory device comprises a memory cell array including a plurality of memory cells, each memory cell corresponding to program data, a data scanning unit to detect the program data having a first value, and a programming unit to program the memory cells corresponding to the detected portions of the program data responsive to the scanning.
摘要翻译：我描述并要求加速位扫描非易失性存储器件和方法。非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，与程序数据相对应的每个存储器单元，用于检测具有第一值的程序数据的数据扫描单元，以及编程单元，用于对与检测到响应于扫描的节目数据的部分。

80. 发明授权

US08971110B2 Nonvolatile memory device and programming method of the same 有权
标题翻译：非易失存储器件和编程方法相同
公开(公告)号：US08971110B2
公开(公告)日：2015-03-03
申请号：US13533999
申请日：2012-06-27
申请人： Sang-Soo Park , Jae-Yong Jeong
发明人： Sang-Soo Park , Jae-Yong Jeong
IPC分类号： G11C11/34 , G11C16/04 , G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3454
摘要： A method is provided for programming a multi-level cell flash memory device. The programming method includes programming a first memory cell of the multi-level call flash memory device to one of first through i-th program states, wherein i is a positive integer, by applying a first program pulse to the first memory cell in a first type programming operation, and programming a second memory cell to one of i+1-th through j-th program states, wherein j is an integer equal to or greater than three, by applying a second program pulse to the second memory cell in a second type programming operation. At least one of a second step voltage, a second bit-line forcing voltage and a second verification operation of the second type programming operation is different from a first step voltage, a first bit-line forcing voltage, and a first verification operation of the first type programming operation, respectively.
摘要翻译：提供了一种用于对多级单元闪存设备进行编程的方法。所述编程方法包括：通过在第一至第i程序状态中的第一至第i程序状态中的第一存储器单元将第一编程脉冲施加到第一存储器单元类型编程操作，并且将第二存储器单元编程为i + 1到第j编程状态之一，其中j是等于或大于3的整数，通过在第二存储器单元中施加第二编程脉冲第二类编程操作。第二阶梯电压，第二位线强制电压和第二类型编程操作的第二验证操作中的至少一个不同于第一阶跃电压，第一位线强制电压和第一验证操作第一类编程操作。

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