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71. 发明授权

US07566651B2 Low contact resistance metal contact 失效
标题翻译：低接触电阻金属接触
公开(公告)号：US07566651B2
公开(公告)日：2009-07-28
申请号：US11692227
申请日：2007-03-28
申请人： Keith Kwong Hon Wong , Chih-Chao Yang , Haining S Yang
发明人： Keith Kwong Hon Wong , Chih-Chao Yang , Haining S Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L21/823418 , H01L21/823475 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region.
摘要翻译：半导体结构及其制作方法。半导体结构包括具有设置在掺杂区域上方的硅化物区域的衬底和延伸穿过硅化物区域并与掺杂区域直接接触的金属接触。

72. 发明申请

US20090148677A1 HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD 失效
标题翻译：高比例电镀金属特征及方法
公开(公告)号：US20090148677A1
公开(公告)日：2009-06-11
申请号：US11953359
申请日：2007-12-10
申请人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
发明人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
IPC分类号： C25D5/02 , B32B3/00
CPC分类号： C25D5/02 , Y10T428/24331 , Y10T428/24917
摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.
摘要翻译：公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料没有接缝和/或空隙。此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

73. 发明授权

US07528451B2 CMOS gate conductor having cross-diffusion barrier 有权
标题翻译： CMOS栅极导体具有交叉扩散势垒
公开(公告)号：US07528451B2
公开(公告)日：2009-05-05
申请号：US11692402
申请日：2007-03-28
申请人： Huilong Zhu , Thomas W. Dyer , Haining S. Yang
发明人： Huilong Zhu , Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/28044 , H01L21/823835 , H01L21/823842 , H01L27/092 , H01L29/78
摘要： A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal.
摘要翻译：为包括具有NFET有源半导体区域的n型场效应晶体管（“NFET”）和具有PFET有源半导体区域的p型场效应晶体管（“PFET”）的晶体管对，提供栅极导体，其中 NFET和PFET有源半导体区域被隔离区隔开。 NFET栅极在NFET有源半导体区域上的第一方向上延伸。 PFET栅极在PFET有源半导体区域上沿第一方向延伸。扩散势垒夹在NFET栅极和PFET栅极之间。连续层在NFET栅极和PFET栅极上在第一方向上连续延伸。连续层接触NFET栅极和PFET栅极的顶表面，并且连续层包括半导体，金属或包括金属的导电化合物中的至少一种。

74. 发明申请

US20090108356A1 INTEGRATION SCHEME FOR MULTIPLE METAL GATE WORK FUNCTION STRUCTURES 失效
标题翻译：多金属门工作功能结构的整合方案
公开(公告)号：US20090108356A1
公开(公告)日：2009-04-30
申请号：US11924053
申请日：2007-10-25
申请人： Kangguo Cheng , Michael P. Chudzik , Rama Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
发明人： Kangguo Cheng , Michael P. Chudzik , Rama Divakaruni , Geng Wang , Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L21/28088 , H01L21/823842 , H01L21/823857 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11 , H01L27/1116 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.
摘要翻译：在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整氧化层。还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。

75. 发明授权

US07504336B2 Methods for forming CMOS devices with intrinsically stressed metal silicide layers 失效
标题翻译：用固定应力金属硅化物层形成CMOS器件的方法
公开(公告)号：US07504336B2
公开(公告)日：2009-03-17
申请号：US11419300
申请日：2006-05-19
申请人： Robert J. Purtell , Henry K. Utomo , Yun-Yu Wang , Haining S. Yang
发明人： Robert J. Purtell , Henry K. Utomo , Yun-Yu Wang , Haining S. Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/324 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/517 , H01L29/665 , H01L29/7845
摘要： The present invention provides a method of fabricating semiconductor device comprising at least one field effect transistor (FET) having source and drain (S/D) metal silicide layers with intrinsic tensile or compressive stress. First, a metal layer containing a silicide metal M is formed over S/D regions of a FET, followed by a first annealing step to form S/D metal silicide layers that comprise a metal silicide of a first phase (MSix). A silicon nitride layer is then formed over the FET, followed by a second annealing step. During the second annealing step, the metal silicide is converted from the first phase (MSix) into a second phase (MSiy) with x
摘要翻译：本发明提供一种制造半导体器件的方法，该方法包括至少一个场效应晶体管（FET），其具有具有固有拉伸或压缩应力的源和漏（S / D）金属硅化物层。首先，在FET的S / D区域上形成含有硅化物金属M的金属层，接着进行第一退火工序，形成包含第一相金属硅化物（MSix）的S / D金属硅化物层。然后在FET上形成氮化硅层，接着进行第二退火步骤。在第二退火步骤期间，金属硅化物从第一相（MSix）转换成具有x

76. 发明申请

US20090039512A1 ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE 审中-公开
标题翻译：电阻互连结构
公开(公告)号：US20090039512A1
公开(公告)日：2009-02-12
申请号：US11835678
申请日：2007-08-08
申请人： Haining S. Yang , Chih-Chao Yang , Keith Kwong Hon Wong
发明人： Haining S. Yang , Chih-Chao Yang , Keith Kwong Hon Wong
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883
摘要： A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls and the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a top surface of the dielectric layer and planarized to form a metal line in the line trench. The metal line is recessed by a recess etch below the top surface of the dielectric layer. A dielectric line cap or a metallic line cap is formed by deposition of a dielectric cap layer or a metallic cap layer, followed by planarization of the dielectric or metallic cap layer. The dielectric line cap or the metallic line cap applies a highly compressive stress on the underlying metal line, which increases electromigration resistance of the metal line.
摘要翻译：在可以包含层间绝缘材料的电介质层中形成线沟槽。金属衬垫形成在线沟槽的侧壁和底表面上。至少在电介质层的顶表面上，在导线沟槽的剩余部分内沉积导电金属，并平坦化以在线沟槽中形成金属线。金属线通过在电介质层的顶表面下方的凹陷蚀刻凹陷。介质线帽或金属线帽通过沉积介质盖层或金属覆盖层，然后平坦化介电层或金属覆盖层而形成。介质线帽或金属线帽在下面的金属线上施加高度压缩应力，这增加了金属线的电迁移阻力。

77. 发明申请

US20090032959A1 ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS 失效
标题翻译：具有分层尺寸的电熔丝和电阻
公开(公告)号：US20090032959A1
公开(公告)日：2009-02-05
申请号：US11831236
申请日：2007-07-31
申请人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
发明人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L27/101 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要翻译：提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。包括导体或半导体的导电结构形成在半导体衬底上。在导电结构上形成至少一个绝缘体层。在所述至少一个绝缘体层中形成凹陷区域。将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

78. 发明授权

US07485508B2 Two-sided semiconductor-on-insulator structures and methods of manufacturing the same 有权
标题翻译：双面绝缘体上半导体结构及其制造方法
公开(公告)号：US07485508B2
公开(公告)日：2009-02-03
申请号：US11627653
申请日：2007-01-26
申请人： Thomas W. Dyer , Haining S. Yang
发明人： Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L21/338
CPC分类号： H01L27/0694 , H01L21/84 , H01L27/1203
摘要： Both sides of a semiconductor-on-insulator substrate are utilized to form MOSFET structures. After forming first type devices on a first semiconductor layer, a handle wafer is bonded to the top of a first middle-of-line dielectric layer. A lower portion of a carrier substrate is then removed to expose a second semiconductor layer and to form second type devices thereupon. Conductive vias may be formed through the buried insulator layer to electrically connect the first type devices and the second type devices. Use of block masks is minimized since each side of the buried insulator has only one type of devices. Two levels of devices are present in the structure and boundary areas between different types of devices are reduced or eliminated, thereby increasing packing density of devices. The same alignment marks may be used to align the wafer either front side up or back side up.
摘要翻译：利用绝缘体上半导体衬底的两侧形成MOSFET结构。在第一半导体层上形成第一类型器件之后，把手晶片结合到第一中间线介电层的顶部。然后移除载体衬底的下部以暴露第二半导体层并在其上形成第二类型器件。可以通过掩埋绝缘体层形成导电孔，以电连接第一类型器件和第二类型器件。掩模掩模的使用最小化，因为埋入绝缘体的每一侧只有一种类型的器件。结构中存在两级装置，减少或消除不同类型装置之间的边界区域，从而提高装置的包装密度。可以使用相同的对准标记来将晶片的前侧向上或向后对准。

79. 发明申请

US20090026543A1 FINFET WITH SUBLITHOGRAPHIC FIN WIDTH 有权
标题翻译： FINFET带子光栅宽度
公开(公告)号：US20090026543A1
公开(公告)日：2009-01-29
申请号：US11828403
申请日：2007-07-26
申请人： Haining S. Yang
发明人： Haining S. Yang
IPC分类号： H01L27/105 , H01L21/8234
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： At least one recessed region having two parallel edges is formed in an insulator layer over a semiconductor layer such that the lengthwise direction of the recessed region coincides with optimal carrier mobility surfaces of the semiconductor material in the semiconductor layer for finFETs to be formed. Self-assembling block copolymers are applied within the at least one recessed region and annealed to form a set of parallel polymer block lines having a sublithographic width and containing a first polymeric block component. The pattern of sublithographic width lines is transferred into the semiconductor layer employing the set of parallel polymer block lines as an etch mask. Sublithographic width semiconductor fins thus formed may have sidewalls for optimal carrier mobility for p-type finFETs and n-type finFETs.
摘要翻译：在半导体层上的绝缘体层中形成具有两个平行边缘的至少一个凹陷区域，使得凹陷区域的长度方向与要形成的鳍状半导体层的半导体层中的半导体材料的最佳载流子迁移率表面重合。自组装嵌段共聚物被施加在所述至少一个凹陷区域内并退火以形成具有亚光刻宽度并包含第一聚合物嵌段组分的一组平行聚合物嵌段体线。使用该组平行聚合物阻挡线作为蚀刻掩模将亚光刻宽度线的图案转移到半导体层中。如此形成的亚光刻宽度半导体鳍片可具有用于p型finFET和n型finFET的最佳载流子迁移率的侧壁。

80. 发明申请

US20090026523A1 PARTIALLY GATED FINFET 有权
标题翻译：部分浇注金属
公开(公告)号：US20090026523A1
公开(公告)日：2009-01-29
申请号：US11782079
申请日：2007-07-24
申请人： Robert C. Wong , Haining S. Yang
发明人： Robert C. Wong , Haining S. Yang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/845 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/785
摘要： A gate dielectric and a gate conductor layer are formed on sidewalls of at least one semiconductor fin. The gate conductor layer is patterned so that a gate electrode is formed on a first sidewall of a portion of the semiconductor fin, while a second sidewall on the opposite side of the first sidewall is not controlled by the gate electrode. A partially gated finFET, that is, a finFET with a gate electrode on the first sidewall and without a gate electrode on the second sidewall is thus formed. Conventional dual gate finFETs may be formed with the inventive partially gated finFETs on the same substrate to provide multiple finFETs having different on-current in the same circuit such as an SRAM circuit.
摘要翻译：在至少一个半导体鳍片的侧壁上形成栅极电介质和栅极导体层。图案化栅极导体层，使得栅极电极形成在半导体鳍片的一部分的第一侧壁上，而在第一侧壁的相对侧上的第二侧壁不受栅电极控制。因此，形成了部分选通的finFET，即在第一侧壁上具有栅电极且在第二侧壁上没有栅电极的finFET。传统的双栅极finFET可以在同一衬底上与本发明的部分选通的鳍状FET形成，以在诸如SRAM电路的同一电路中提供具有不同导通电流的多个finFET。

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