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71. 发明授权

US07160774B2 Method of forming polysilicon layers in non-volatile memory 有权
标题翻译：在非易失性存储器中形成多晶硅层的方法
公开(公告)号：US07160774B2
公开(公告)日：2007-01-09
申请号：US10870285
申请日：2004-06-16
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21/336
CPC分类号： H01L29/4916 , H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.
摘要翻译：根据本发明的实施例，半导体结构包括未掺杂多晶硅层，与未掺杂多晶硅层接触的掺杂多晶硅层，以及与未掺杂多晶硅层接触的绝缘层。未掺杂的多晶硅层夹在掺杂多晶硅层和绝缘层之间。

72. 发明授权

US06812515B2 Polysilicon layers structure and method of forming same 有权
标题翻译：多晶硅层的结构及其形成方法
公开(公告)号：US06812515B2
公开(公告)日：2004-11-02
申请号：US09994545
申请日：2001-11-26
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L29788
CPC分类号： H01L29/4916 , H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.
摘要翻译：非易失性存储单元包括在衬底区域上的第一绝缘层和浮置栅极。浮置栅极包括在第一绝缘层之上的第一多晶硅层和在第一多晶硅层上并与第一多晶硅层接触的第二多晶硅层。第一多晶硅层具有预定的掺杂浓度，并且第二多晶硅层具有在远离第一和第二多晶硅层之间的界面的方向上减小的掺杂浓度。第二绝缘层覆盖并与第二多晶硅层接触。控制栅极包括在第二绝缘层上并与第二绝缘层接触的第三多晶硅层，以及在第三多晶硅层上并与第三多晶硅层接触的第四多晶硅层。第四多晶硅层具有预定的掺杂浓度，并且第三多晶硅层具有在远离第三和第四多晶硅层之间的界面的方向上减小的掺杂浓度。

73. 发明授权

US06559008B2 Non-volatile memory cells with selectively formed floating gate 有权
公开(公告)号：US06559008B2
公开(公告)日：2003-05-06
申请号：US09971434
申请日：2001-10-04
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.

74. 发明授权

US5989938A Method of fabricating topside structure of a semiconductor device 失效
标题翻译：制造半导体器件的顶侧结构的方法
公开(公告)号：US5989938A
公开(公告)日：1999-11-23
申请号：US926583
申请日：1997-09-04
申请人： Hsingya Arthur Wang , Bandali B. Mohamed , Shyam Garg , Bruce Pickelsimer
发明人： Hsingya Arthur Wang , Bandali B. Mohamed , Shyam Garg , Bruce Pickelsimer
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/314 , H01L21/316 , H01L21/8247 , H01L23/29 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/44 , H01L21/00 , H01L21/48
CPC分类号： H01L21/3144 , H01L21/31053 , H01L23/291 , H01L2924/0002 , Y10S428/901 , Y10T428/24917 , Y10T428/24926
摘要： The present method and apparatus provides a thin layer of oxynitride over a device including a patterned metal layer, application of a planarizing SOG layer over the thin oxynitride layer, removal of thin portions of the SOG layer by etching to expose portions of the thin oxynitride layer, and application of a thick oxynitride layer to form a strong bond with the thin oxynitride layer. A thin nitride layer, transparent to UV light, may then be applied to the resulting structure prior to application of plastic packaging material.
摘要翻译：本方法和装置在包括图案化金属层的装置上提供氧氮化钛薄层，在薄氧氮化物层上施加平坦化SOG层，通过蚀刻去除薄的部分SOG层，以暴露部分薄氮氧化物层以及施加厚的氧氮化物层以与薄氮氧化物层形成强结合。然后可以在施加塑料包装材料之前将对UV光透明的薄氮化物层施加到所得到的结构。

75. 发明授权

US5920506A Method and apparatus for bulk preprogramming flash memory cells with minimal source and drain currents 失效
标题翻译：用于批量预编程具有最小源极和漏极电流的闪存单元的方法和装置
公开(公告)号：US5920506A
公开(公告)日：1999-07-06
申请号：US938389
申请日：1997-09-26
申请人： Hsingya Arthur Wang , Haike Dong , Jein-Chen Young , Yuan Tang , Aaron Yip , Kenneth Miu
发明人： Hsingya Arthur Wang , Haike Dong , Jein-Chen Young , Yuan Tang , Aaron Yip , Kenneth Miu
IPC分类号： G11C16/10 , G11C16/16 , G11C16/04
CPC分类号： G11C16/107 , G11C16/10 , G11C16/16 , G11C2216/16
摘要： Apparatus is provided to facilitate the process of bulk preprogramming each of the cells in a flash memory or a subblock of a flash memory. In the process, the source and drain of each cell to be preprogrammed is biased such that current need not be flowing between the source and drain through the cell's channel region for charge to be transferred between the cell's channel region and the cell's floating gate. In a specific embodiment, the sources and drains are left floating without any particular bias voltage and the control gates of the cells are set to between 9 and 12 volts above the substrate and held there for about 10 milliseconds (ms). In an alternate embodiment, the sources and drains of all of the cells to be preprogrammed are biased to the same potential, which is a negative voltage, ground, or a positive voltage.
摘要翻译：提供了设备以便于批量预编程闪速存储器或闪速存储器的子块中的每个单元的处理。在该过程中，要预编程的每个单元的源极和漏极被偏置，使得电流不需要在源极和漏极之间通过电池的沟道区域流动，以在电池的沟道区域和电池的浮动栅极之间传输电荷。在具体实施例中，源极和漏极在没有任何特定偏置电压的情况下保持浮置，并且单元的控制栅极被设置在衬底上方9到12伏之间并保持在大约10毫秒（ms）。在替代实施例中，要预编程的所有单元的源极和漏极被偏置到相同的电位，其是负电压，接地或正电压。

76. 发明授权

US5908318A Method of forming low capacitance interconnect structures on semiconductor substrates 失效
标题翻译：在半导体衬底上形成低电容互连结构的方法
公开(公告)号：US5908318A
公开(公告)日：1999-06-01
申请号：US932288
申请日：1997-09-17
申请人： Hsingya Arthur Wang , David Michael Rogers
发明人： Hsingya Arthur Wang , David Michael Rogers
IPC分类号： H01L21/768 , H01L21/441
CPC分类号： H01L21/7682
摘要： Disclosed herein is a method for forming an interconnect line having low conductor line capacitance between devices formed on an integrated circuit. The method comprises the steps of depositing a removable planarizing layer over fabricated device on the integrated circuit, depositing a first oxide layer over the planarizing layer, etching pillar shafts through the planarizing layer and the first oxide layer for the formation of pillars, depositing a second oxide layer over the first oxide layer filling the pillar shafts to form the pillars, etching contact shafts through the planarizing layer, the first oxide layer, and the second oxide layer to expose contacts for a first device and a second device formed on the integrated circuit, forming an electrical coupling between the contacts of the first device and the second device, etching through the planarizing layer, the first oxide layer, and the second oxide layer to provide accesses to the planarizing layer, removing the planarizing layer to form cavities separated by the pillars and the contact shafts, sealing the accesses to the cavities with a third oxide layer, and introducing an inert ambiance while sealing the accesses to the cavities whereby the dielectric constant of the cavities surrounding the interconnect line is approximately that of the inert ambiance.
摘要翻译：这里公开了一种在集成电路上形成的器件之间形成具有低导体线电容的互连线的方法。该方法包括以下步骤：在集成电路上的制造的器件上沉积可移除的平坦化层，在平坦化层上沉积第一氧化物层，蚀刻通过平坦化层的柱轴和用于形成柱的第一氧化物层，在所述第一氧化物层上方填充柱状物以形成所述柱，通过所述平坦化层，所述第一氧化物层和所述第二氧化物层蚀刻接触轴，以暴露出用于形成在所述集成电路上的第一器件和第二器件的触点在所述第一器件和所述第二器件的触点之间形成电耦合，蚀刻通过所述平坦化层，所述第一氧化物层和所述第二氧化物层以提供对所述平坦化层的访问，去除所述平坦化层以形成由支柱和接触轴，用第三氧化物层密封对腔的通路，并引入同时密封对空腔的访问，由此围绕互连线的空腔的介电常数大约是惰性气氛的介电常数。

77. 发明授权

US5763307A Block select transistor and method of fabrication 失效
标题翻译：块选择晶体管及其制造方法
公开(公告)号：US5763307A
公开(公告)日：1998-06-09
申请号：US745278
申请日：1996-11-08
申请人： Hsingya Arthur Wang , Qimeng Zhou
发明人： Hsingya Arthur Wang , Qimeng Zhou
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11534
摘要： A flash memory device having a reduced area is disclosed. The device uses a polyI layer to act as a select transistor for the memory cells comprising the core array. Also, a ground plate is used to isolate the areas of the memory array where high voltage devices should not be located, thereby allowing peripheral components to be fabricated in the core array area. Also disclosed is a polyII layer used to access two sublines controlling two different sectors of the memory array architecture. By using such a layout, die space savings is attained.
摘要翻译：公开了一种具有减小的面积的闪速存储器件。该器件使用polyI层作为包括核心阵列的存储器单元的选择晶体管。此外，接地板用于隔离存储器阵列中不应该位于高电压器件的区域，从而允许在核心阵列区域中制造外围元件。还公开了用于访问控制存储器阵列架构的两个不同扇区的两个子线的polyII层。通过使用这种布局，可以节省模具空间。

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