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    • 72. 发明授权
    • Micro crossbar switch and on-die data network using the same
    • 微型交叉开关和片上数据网络使用相同
    • US08583850B2
    • 2013-11-12
    • US13026582
    • 2011-02-14
    • Robert P. MasleidThirumalai Suresh
    • Robert P. MasleidThirumalai Suresh
    • G06F13/00G06F13/40
    • G06F13/4022
    • An integrated circuit (IC) having an on-die data network is disclosed. The IC includes a first bus and second buses configured to convey signals in first and second directions, respectively, along a first axis. The second direction is opposite the first. The IC further includes third and fourth buses configured to convey signals in third and fourth directions, respectively, along a second axis perpendicular to the first axis. The fourth direction is opposite the third. Each bus is N-bits wide and unidirectional. Signal lines of two different buses having equal bit significance and opposite direction are arranged adjacent to one another. A crossbar unit having N crossbar switching circuits is configured to couple signal lines of a selected one of the buses to a corresponding signal line of another selected one of the buses. The signal lines of the buses are implemented on different metal layers than the crossbar switching circuits.
    • 公开了一种具有片上数据网络的集成电路(IC)。 IC包括第一总线和第二总线,其被配置为沿着第一轴分别沿第一和第二方向传送信号。 第二个方向与第一个方向相反。 IC还包括分别沿垂直于第一轴线的第二轴线沿第三和第四方向传送信号的第三和第四总线。 第四个方向与第三个方向相反。 每个总线是N位宽和单向。 具有相同位意义和相反方向的两个不同总线的信号线彼此相邻布置。 具有N个交叉开关电路的交叉开关单元被配置为将所选择的一个总线的信号线耦合到另一所选总线的相应信号线。 总线的信号线在与交叉开关电路不同的金属层上实现。
    • 73. 发明授权
    • Adaptive synchronization circuit
    • 自适应同步电路
    • US08559576B2
    • 2013-10-15
    • US12193609
    • 2008-08-18
    • Tarik OnoMark R. Greenstreet
    • Tarik OnoMark R. Greenstreet
    • H04L7/00
    • H04L7/02G06F5/10H04L7/005H04L7/0083H04L7/0091
    • Embodiments of a synchronization circuit are described. This synchronization circuit includes multiple selectively coupled synchronization stages which are configurable to synchronize data and control signals between a first time domain and a second time domain, where the synchronization can be performed based on asynchronous or synchronous events associated with either the first time domain or the second time domain. Additionally, the synchronization circuit includes control logic, coupled to the synchronization stages, which is configured to adapt a number of synchronization stages used to synchronize the data and the control signals based on an estimate of a probability of metastability persisting to an output of the synchronization circuit during the synchronization.
    • 描述同步电路的实施例。 该同步电路包括多个选择性耦合的同步级,其可配置为在第一时域和第二时域之间同步数据和控制信号,其中可以基于与第一时域或第二时域相关联的异步或同步事件执行同步 第二时间域 另外,同步电路包括耦合到同步级的控制逻辑,其被配置为基于用于同步数据和控制信号的多个同步级,所述同步级基于持续到同步输出的亚稳定概率的估计 电路在同步期间。
    • 80. 发明授权
    • Method and system for self-tuning of hardware resources
    • 硬件资源自调整方法及系统
    • US08516503B2
    • 2013-08-20
    • US12688803
    • 2010-01-15
    • Eric C. SaxeDarrin P. Johnson
    • Eric C. SaxeDarrin P. Johnson
    • G06F3/00G06F9/44G06F9/46G06F13/00G06F9/00G06F1/24
    • G06F9/5011G06F11/3409G06F11/3466G06F2201/81G06F2201/885
    • A system for self-tuning hardware resources includes a processor, a hardware resource, an operating system (OS), a metric monitoring unit (MMU), and a configuration engine (CE). The OS determines: the hardware resource; a metric for monitoring the hardware resource; a hardware resource management policy for the hardware resource; and a primary and secondary sub-ranges for the metric. The OS sends a hardware resource management policy directive to the CE. The MMU monitors the hardware resource to obtain data for the metric. The CE receives the hardware resource management policy directive, determines the primary and secondary sub-ranges from the hardware resource management policy directive, obtains data for the metric from the MMU. When data is outside the primary sub-range and inside the secondary sub-range, the CE determines and executes a hardware resource optimization routine to bring hardware resource utilization into compliance with the primary sub-range.
    • 用于自调谐硬件资源的系统包括处理器,硬件资源,操作系统(OS),度量监视单元(MMU)和配置引擎(CE)。 操作系统确定:硬件资源; 用于监控硬件资源的度量; 硬件资源的硬件资源管理策略; 以及度量的主要和次要子范围。 OS向CE发送硬件资源管理策略指令。 MMU监视硬件资源以获取度量的数据。 CE接收硬件资源管理策略指令,从硬件资源管理策略指令确定主,副子范围,从MMU获取度量值的数据。 当数据位于主子范围以外的次级子范围内时,CE确定并执行硬件资源优化例程,使硬件资源利用符合主要子范围。